Advanced loop parallelization and integrated vectorization
| Project/Area Number |
18K18032
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| Research Category |
Grant-in-Aid for Early-Career Scientists
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| Allocation Type | Multi-year Fund |
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| Review Section |
Basic Section 60050:Software-related
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| Research Institution | The University of Tokyo |
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Principal Investigator |
Sato Shigeyuki 東京大学, 大学院情報理工学系研究科, 助教 (90779464)
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| Project Period (FY) |
2018-04-01 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2020: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2019: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2018: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
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| Keywords | プログラム合成 / 自動並列化 / コンパイラ / ループ並列化 / ベクトル化 |
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| Outline of Final Research Achievements |
In this project, we studied automatic parallelization of complicated reduction loops. Our developed techniques enable us to systematically transform serial intuitive specifications into divide-and-conquer implementations amenable to various parallel computers. Specifically, we developed 1) a branch elimination method by operator extraction, 2) a parallelization method based on dynamic behaviors, and 3) a vectorization method based on data shuffling as part of the fundamental compiler technology. To evaluate these techniques, we also developed 4) a benchmark suite of reduction loops. Furthermore, we developed implementation techniques for 5) parallel lexing and 6) parallel regular expression matching as case studies on applications of complicated reductions.
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| Academic Significance and Societal Importance of the Research Achievements |
今日において，既にさまざまな並列計算機が至る所にあると同時に，新しい並列計算機が次々と開発されている．その並列計算機のハードウェア性能を引き出すには，並列プログラムが必要になる．しかし，並列プログラムを上手く作ることは人間にはとても難しく，しばしば，間違った計算をしたり，性能が悪くなったりする．本研究で扱った自動並列化技術は，人間にとって直観的で間違えにくい計算仕様を，並列計算機に都合が良い計算形式に変換するものである．これにより，多様な並列計算機のハードウェア性能を，簡単かつ安全に引き出すことができるようになる．
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Report
(5 results)
Research Products
(5 results)
