A Study of Matrix Multiply by Homomorphic Encryption for Utilizing in Deep Learning Frameworks

• Project/Area Number: 18K19786
• Research Category: Grant-in-Aid for Challenging Research (Exploratory)
• Allocation Type: Multi-year Fund
• Review Section: Medium-sized Section 60:Information science, computer engineering, and related fields
• Research Institution: Waseda University
• Principal Investigator: Kimura Keiji 早稲田大学, 理工学術院, 教授 (50318771)
• Co-Investigator(Kenkyū-buntansha): 和田 康孝 明星大学, 情報学部, 准教授 (40434310)
• Project Period (FY): 2018-06-29 – 2020-03-31
• Project Status: Completed (Fiscal Year 2019)
• Budget Amount: ¥6,370,000 (Direct Cost: ¥4,900,000、Indirect Cost: ¥1,470,000); Fiscal Year 2019: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000); Fiscal Year 2018: ¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
• Keywords: 秘密計算 / 準同型暗号 / 高速化 / マルチコア / アクセラレータ / FPGA / 完全準同型暗号 / 行列積

Outline of Final Research Achievements

This research aims at accelerating matrix-multiply in homomorphic encryption toward utilizing it in deep learning frameworks. Through the research, we obtained 5.53x and 3.73x speedups in maximum for two important computational parts in the target encrypted matrix-multiply process. In addition, we have developed a data transfer unit, which can quickly provide required data to accelerator hardware units. We also investigated and evaluated the relationship between the precision of computations and calculation time to reduce the calculation cost while keeping the appropriate precision. As a result, we obtained 8 points accuracy improvement and 54% speedup for image recognition at the same time by parallel inference with eight smaller neural networks.

Academic Significance and Societal Importance of the Research Achievements

準同型暗号により暗号化したまま計算可能なことで、秘密を保ったままクラウドなどの第三者環境にデータを提供し安全に計算処理を行うことができるようになったが、その計算コストが極めて大きいことが問題となっていた。本研究により得られた成果により、準同型暗号による行列積の処理を高速化可能となる。行列積は深層学習処理の主たる計算要素であるため、秘密を保ったままにしてクラウドで深層学習処理（主に推論処理を想定）を行い、結果を安全に利用者に返すことが可能となる。

Research Products

• [Int'l Joint Research] E-JUST(エジプト)
• [Int'l Joint Research] エジプト日本科学技術大学(エジプト)
• [Journal Article] Local Memory Mapping of Multicore Processors on an Automatic Parallelizing Compiler (2020)
  • Author(s): Yoshitake OKI, Yuto ABE, Kazuki YAMAMOTO, Kohei YAMAMOTO, Tomoya SHIRAKAWA, Akimasa YOSHIDA, Keiji KIMURA, Hironori KASAHARA
  • Journal Title: IEICE Transactions on Electronics Volume: E103.C Issue: 3 Pages: 98-109
  • DOI: 10.1587/transele.2019LHP0010
  • NAID: 130007804176
  • ISSN: 0916-8524, 1745-1353
  • Year and Date: 2020-03-01
  • Peer Reviewed
• [Journal Article] Compiler Software Coherent Control for Embedded High Performance Multicore (2020)
  • Author(s): Boma A. ADHI, Tomoya KASHIMATA, Ken TAKAHASHI, Keiji KIMURA, Hironori KASAHARA
  • Journal Title: IEICE Transactions on Electronics Volume: E103.C Issue: 3 Pages: 85-97
  • DOI: 10.1587/transele.2019LHP0008
  • NAID: 130007804174
  • ISSN: 0916-8524, 1745-1353
  • Year and Date: 2020-03-01
  • Peer Reviewed
• [Journal Article] Compiler-support for Critical Data Persistence in NVM (2020)
  • Author(s): Reem Elkhouly, Mohammad Alshboul, Akihiro Hayashi, Yan Solihin, Keiji Kimura
  • Journal Title: ACM Transactions on Architecture and Code Optimization (TACO) Volume: 16 Issue: 4 Pages: 1-25
  • DOI: 10.1145/3371236
  • Peer Reviewed / Open Access / Int'l Joint Research
• [Journal Article] Efficient Checkpointing with Recompute Scheme for Non-volatile Main Memory (2019)
  • Author(s): Mohammad Alshboul, Hussein Elnawawy, Reem Elkhouly, Keiji Kimura, James Tuck, Yan Solihin
  • Journal Title: ACM Transactions on Architecture and Code Optimization (TACO) Volume: 16 Issue: 2 Pages: 1-27
  • DOI: 10.1145/3323091
  • Peer Reviewed / Open Access / Int'l Joint Research
• [Presentation] 準同型暗号による行列積の高速化の検討 (2020)
  • Author(s): 牧田 哲也, 宍戸 哲平, 和田 康孝, 木村 啓二
  • Organizer: 電子情報通信学会技術報告, CPSY2019-96,DC2019-102(2020-02) (ETNET2020)
• [Presentation] NDCKPT:不揮発性メインメモリを用いたOSによる透過的なプロセスチェックポインティングの実現 (2020)
  • Author(s): 西田 耀, 木村 啓二
  • Organizer: 電子情報通信学会技術報告, CPSY2019-102,DC2019-108(2020-02) (ETNET2020)
• [Presentation] OSCARコンパイラのC++プログラム対応の検討 (2020)
  • Author(s): 川角 冬馬, TilmanPriesner, 野口 真聖, 韓 吉新, 見神 広紀, 川島 慧大, 田中啓士郎, 木村 啓二, 笠原 博徳
  • Organizer: 電子情報通信学会技術報告, CPSY2019-110,DC2019-116(2020-02) (ETNET2020)
• [Presentation] マルチターゲット自動並列化コンパイラにおけるアクセラレータコスト推定手法の検討 (2020)
  • Author(s): 山本 一貴, 藤田 一輝, 柏俣 智哉, 高橋 健, Boma A. Adhi, 北村 俊明, 川島 慧大, 納富 昭, 森 裕司, 木村 啓二, 笠原 博徳
  • Organizer: 情報処理学会研究会, Vol.2019-ARC-240 No.25, Vol.2019-SLDM-191 No.25, Vol.2019-EMB-53 No.25 (ETNET2020)
• [Presentation] OSCAR自動並列化コンパイラとNECベクトル化コンパイラの協調によるベクトル・パーソナルスパコン上での自動ベクトル並列化 (2020)
  • Author(s): 田處 雄大, 見神 広紀, 細見 岳生, 木村 啓二, 笠原 博徳
  • Organizer: 情報処理学会研究会, Vol.2019-ARC-240 No.26, Vol.2019-SLDM-191 No.26, Vol.2019-EMB-53 No.26 (ETNET2020)
• [Presentation] FPGA上でのCNNパラメータ動的更新手法の性能評価 (2020)
  • Author(s): 青戸 武蔵, 和田 康孝, 三ツ木 萌
  • Organizer: 情報処理学会 第82回全国大会
• [Presentation] Fast and Highly Optimizing Separate Compilation for Automatic Parallelization (2019)
  • Author(s): Tohma Kawasumi, Ryota Tamura, Yuya Asada, Jixin Han, Hiroki Mikami, Keiji Kimura , Hironori Kasahara
  • Organizer: The 2019 International Conference on High Performance Computing & Simulation (HPCS 2019)
  • Int'l Joint Research
• [Presentation] Performance Evaluation on NVMM Emulator Employing Fine-Grain Delay Injection (2019)
  • Author(s): Yu Omori, Keiji Kimura
  • Organizer: The 8th IEEE Non-Volatile Memory Systems and Applications Symposium (IEEE NVMSA 2019)
  • Int'l Joint Research
• [Presentation] Performance of Static and Dynamic Task Scheduling for Real-Time Control System on Embedded Multicore Processor (2019)
  • Author(s): Yoshitake Oki, Hiroki Mikami, Hikaru Nishida, Dan Umeda, Keiji Kimura, Hironori Kasahara
  • Organizer: 32nd International Workshop on Languages and Compilers for Parallel Computing(LCPC)
  • Int'l Joint Research
• [Presentation] Cascaded DMA Controller for Speedup of Indirect Memory Access in Irregular Applications (2019)
  • Author(s): Tomoya Kashimata, Toshiaki Kitamura, Keiji Kimura, Hironori Kasahara
  • Organizer: 9th Workshop on Irregular Applications: Architectures and Algorithms
  • Int'l Joint Research
• [Presentation] Cascaded DMAC Enabling Efficient Data Transfer for Indirect Memory Access Applications (2019)
  • Author(s): Keiji Kimura
  • Organizer: 4th International Symposium on Research and Education of Computational Science (RECS)
  • Invited
• [Presentation] Towards the Improvement of Training Efficiency and Image Recognition Accuracy for an FPGA Controlled Mini-Car by Offloading Neural Network Training (2019)
  • Author(s): Musashi Aoto, Moe Mitsugi, Takumi Momose, and Yasutaka Wada
  • Organizer: Proc. of The 2019 International Conference on Field-Programmable Technology (FPT2019), FPGA Design Competition
  • Int'l Joint Research
• [Presentation] 単機能なニューラルネットワークを複数用いた高速・高精度な画像認識のFPGAによる実現 (2019)
  • Author(s): 青戸 武蔵, 比留川 翔哉, 和田 康孝, 丸山 一貴
  • Organizer: RECONF2019-31
• [Presentation] An FPGA based Autonomous Driving Car Design using Multiple Simple Neural Networks for Decision Making (2019)
  • Author(s): Musashi Aoto, Shoya Hirukawa, Yasutaka Wada, Kazutaka Maruyama
  • Organizer: The Tenth International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies (HEART2019) FPGA Design Contest
  • Int'l Joint Research
• [Presentation] DMAのカスケード接続による間接ロードの高速化 (2019)
  • Author(s): 柏俣 智哉 、北村 俊明、木村 啓二、笠原 博徳
  • Organizer: 情報処理学会 第226回 システム・アーキテクチャ研究発表会
• [Remarks] 木村研究室・発表論文
  • URL: http://www.apal.cs.waseda.ac.jp/kimura/achieves.html