Desigin methodologies for measurement-based quantum circuits

• Project/Area Number: 18K19790
• Research Category: Grant-in-Aid for Challenging Research (Exploratory)
• Allocation Type: Multi-year Fund
• Review Section: Medium-sized Section 60:Information science, computer engineering, and related fields
• Research Institution: Ritsumeikan University
• Principal Investigator: Yamashita Shigeru 立命館大学, 情報理工学部, 教授 (30362833)
• Project Period (FY): 2018-06-29 – 2022-03-31
• Project Status: Completed (Fiscal Year 2021)
• Budget Amount: ¥6,240,000 (Direct Cost: ¥4,800,000、Indirect Cost: ¥1,440,000); Fiscal Year 2020: ¥2,730,000 (Direct Cost: ¥2,100,000、Indirect Cost: ¥630,000); Fiscal Year 2019: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000); Fiscal Year 2018: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
• Keywords: 量子回路設計 / 測定型量子回路 / braiding / lattice Surgery / T`ゲート / Relative Phase量子ゲート / 最適化 / RTOFゲート / Tゲート / lattice srurgery / 自由度 / トポロジカル量子回路 / bridge / トーラス / 設計理論

Outline of Final Research Achievements

One of the promissing ways of realizing quantum computation is measurement-based quantum circuits. For the design methodolgoy of measurement-based quantum circuits, this research got the following results. (1) This reseach developped an automatic circuit reduction method by representing a seaquence of braiding operations for measurement-based quantum circuits with toruses. (2) This research develloped a method to reduce the circuit size by the layout of logical qubits for the lattice surgery model which represents a measurement-based quantum circuit. The method can reduce the final circuit size compared to the conventional methods. (3) This research developped a various optimization methods to decrease the number of T gates whose realization costs are very high for measurement-based quantum circuits.

Academic Significance and Societal Importance of the Research Achievements

量子計算はまだ完全には実現されていない。しかし、もし量子計算機が実現すれば、ある種の有用な問題で現在の計算機では時間がかかりすぎて到底計算できないような問題を、現実的な時間で計算できるようになると期待されている。しかし、量子計算は物理的なエラーに弱く、それを克服する有用な実現方法が、測定型量子回路と呼ばれるものである。測定型量子回路は通常の量子回路とモデルが違うため、その設計手法を確立することは将来の量子計算の実現のために大変重要であると考えられる。本研究の成果は、測定型量子回路の設計手法に関して今まで知られていなかった新しい設計手法として今後利用できることが期待できる。

Research Products

• [Journal Article] Optimization Problems in Quantum Circuit Design (2021)
  • Author(s): YAMASHITA Shigeru
  • Journal Title: IEICE ESS Fundamentals Review Volume: 14 Issue: 4 Pages: 337-346
  • DOI: 10.1587/essfr.14.4_337
  • NAID: 130008020108
  • ISSN: 1882-0875
  • Year and Date: 2021-04-01
  • Peer Reviewed / Open Access
• [Journal Article] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures (2021)
  • Author(s): Atsushi Matsuo, Wakaki Hattori, Shigeru Yamashita
  • Journal Title: IEEE 26th Asia and South Pacific Design Automation Conference Volume: ASP-DAC2021 Pages: 786-791
  • Peer Reviewed
• [Journal Article] Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems (2020)
  • Author(s): Atsushi Matsuo, Yudai Suzuki, Shigeru Yamashita
  • Journal Title: The 20th Asian Quantum Information Science Conference Volume: AQIS2020 Pages: 161-161
  • Peer Reviewed
• [Journal Article] Quantum Circuit Design by Steiner-Gauss with Considering the Order of Qubits (2020)
  • Author(s): HAN Zhengtong, Shigeru Yamashita
  • Journal Title: The 20th Asian Quantum Information Science Conference Volume: AQIS2020 Pages: 188-188
  • Peer Reviewed
• [Journal Article] An Efficient Generation of Arbitrary Superposition of Basis States (2020)
  • Author(s): Risa Segawa, Shigeru Yamashita
  • Journal Title: The 20th Asian Quantum Information Science Conference Volume: AQIS2020 Pages: 211-211
  • Peer Reviewed
• [Journal Article] Mapping a Quantum Circuit to 2D Nearest Neighbor Architecture by Changing the Gate Order (2019)
  • Author(s): Wakaki Hattori, Shigeru Yamashita
  • Journal Title: IEICE Transactions on Information and Systems Volume: E102.D Issue: 11 Pages: 2127-2134
  • DOI: 10.1587/transinf.2018EDP7439
  • NAID: 130007740443
  • ISSN: 0916-8532, 1745-1361
  • Year and Date: 2019-11-01
  • Peer Reviewed
• [Journal Article] Automatic Optimization Methodology for Large-Scale TQEC Circuits (2019)
  • Author(s): 浅井孝太, 星孝太郎, 山下茂
  • Journal Title: 電子情報通信学会論文誌D 情報・システム Volume: J102-D Issue: 5 Pages: 367-377
  • DOI: 10.14923/transinfj.2018JDP7040
  • ISSN: 1880-4535, 1881-0225
  • Year and Date: 2019-05-01
  • Peer Reviewed
• [Journal Article] Compaction of Topological Quantum Circuits by Modularization (2019)
  • Author(s): Kota Asahi and Shigeru Yamashita
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: E102.A Issue: 4 Pages: 624-632
  • DOI: 10.1587/transfun.E102.A.624
  • NAID: 130007621576
  • ISSN: 0916-8508, 1745-1337
  • Year and Date: 2019-04-01
  • Peer Reviewed
• [Journal Article] Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2D architecture and its Application to Large-scale Circuits (2019)
  • Author(s): Jingwen Ding and Shigeru Yamashita
  • Journal Title: IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems Volume: 1 Issue: 5 Pages: 1-1
  • DOI: 10.1109/tcad.2019.2907919
  • Peer Reviewed
• [Journal Article] Quantum Circuit Optimization by Changing the Gate Order for 2D Nearest Neighbor Architectures (2018)
  • Author(s): Wakaki Hattori and Shigeru Yamashita
  • Journal Title: Lecture Notes in Computer Science Volume: 11106 Pages: 228-243
  • DOI: 10.1007/978-3-319-99498-7_16
  • ISBN: 9783319994970, 9783319994987
  • Peer Reviewed
• [Journal Article] 量子回路設計と最適化 (2018)
  • Author(s): 山下茂，松尾惇士
  • Journal Title: オペレーションズ・リサーチ Volume: Vol.63, No.6 Pages: 342-349
• [Presentation] Exact Minimization of a Relative-Phase Toffoli Gate (2022)
  • Author(s): Naoya Asada
  • Organizer: 25th Annual Conference on Quantum Information Processing
  • Int'l Joint Research
• [Presentation] Optimization of Quantum Boolean Circuits by Relative-Phase Toffoli Gates (2022)
  • Author(s): Shouhei Kuroda
  • Organizer: Reversible Computation 2022
  • Int'l Joint Research
• [Presentation] Dynamical Decomposition and Mapping of MPMCT Gates to Nearest Neighbor Architectures (2021)
  • Author(s): Atsushi Matsuo
  • Organizer: 26th IEEE Asia and South Pacific Design Automation Conference (ASP-DAC2021)
  • Int'l Joint Research
• [Presentation] 位相がずれたToffoliゲートの厳密最小化手法 (2021)
  • Author(s): 浅田尚也
  • Organizer: 第45回量子情報技術研究会
  • Int'l Joint Research
• [Presentation] A Cost Reduction Method for Quantum Boolean Circuits by Applying The Transduction Method (2021)
  • Author(s): Shohei Kuroda
  • Organizer: Asian Quantum Information Science Conference 2021
  • Int'l Joint Research
• [Presentation] Quantum State Preparation By Gaussian Elimination (2021)
  • Author(s): Duo Xu
  • Organizer: Asian Quantum Information Science Conference 2021
  • Int'l Joint Research
• [Presentation] T-depth Reduction Considering Multiple MCT Gates with Ancilla Bits (2021)
  • Author(s): Terumi Oguri
  • Organizer: Asian Quantum Information Science Conference 2021
  • Int'l Joint Research
• [Presentation] 量子回路の設計手法に関する研究動向 (2020)
  • Author(s): 山下 茂
  • Organizer: 情報処理学会連続セミナー2020 量子コンピュータとソフトウェア2020
  • Invited
• [Presentation] 量子回路設計 (2020)
  • Author(s): 山下 茂
  • Organizer: 情報処理学会 量子ソフトウェア研究会月例バーチャルセミナー
  • Invited
• [Presentation] 量子ソフトウエア研究会の紹介とSLDM研究会との連携の期待 (2020)
  • Author(s): 山下 茂
  • Organizer: 情報処理学会 DAシンポジウム 2020
  • Invited
• [Presentation] 量子ビットの処理順序を考慮したシュタイナーガウス消去法による量子回路の設計 (2020)
  • Author(s): HAN ZHENGTONG
  • Organizer: デザインガイア2020
• [Presentation] Problem-specific Parameterized Quantum Circuits of the VQE Algorithm for Optimization Problems (2020)
  • Author(s): Atsushi Matsuo
  • Organizer: 情報処理学会第1回量子ソフトウェア研究発表会
• [Presentation] 量子回路設計 (2019)
  • Author(s): 山下茂
  • Organizer: 第18回情報科学技術フォーラム（FIT）イベント企画：量子コンピュータ技術基盤の創出に向けて
  • Invited
• [Presentation] 量子回路設計における最適化問題 (2019)
  • Author(s): 山下茂
  • Organizer: 電子情報通信学会 VLD研究会
  • Invited
• [Presentation] An Efficient Method for Quantum Circuit Placement Problem on a 2-D Grid (2019)
  • Author(s): Shigeru Yamashita
  • Organizer: Reversible Computation 2019
  • Int'l Joint Research
• [Presentation] A handy condition of bridge compression for topological quantum circuits (2019)
  • Author(s): Yohei Wakabayashi
  • Organizer: 19th Asian Quantum Information Science Conference
  • Int'l Joint Research
• [Presentation] Minimizing Quantum Circuits for Simultaneous Two-Qubit Measurement by Single-Qubit Measurements (2019)
  • Author(s): Risa Segawa
  • Organizer: 19th Asian Quantum Information Science Conference
  • Int'l Joint Research
• [Presentation] Efficient Mapping of the ZX calculus (2019)
  • Author(s): Kota Asai
  • Organizer: 19th Asian Quantum Information Science Conference
  • Int'l Joint Research
• [Presentation] The decomposition of an MPMCT gate in consideration of NNA (2019)
  • Author(s): Wakaki Hattori
  • Organizer: 19th Asian Quantum Information Science Conference
  • Int'l Joint Research
• [Presentation] Exact and Approximate Exact Synthesis of Nearest Neighbor Compliant Quantum Circuits in 2-D Architectures (2018)
  • Author(s): Jingwen Ding
  • Organizer: AQIS 2018
  • Int'l Joint Research
• [Presentation] Compaction of Topological Quantum Circuits by Modularization (2018)
  • Author(s): Kota Asai and Shigeru Yamashita
  • Organizer: AQIS 2018
  • Int'l Joint Research
• [Presentation] Mapping to 2D Nearest Neighbor Architecture by a SAT Solver and A* Algorithm (2018)
  • Author(s): Wakaki Hattori and Shigeru Yamashita
  • Organizer: AQIS 2018
  • Int'l Joint Research