| Project/Area Number |
19360165
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Tohoku Gakuin University |
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Principal Investigator |
HARA Akito Tohoku Gakuin University, 工学部, 教授 (20417398)
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| Co-Investigator(Kenkyū-buntansha) |
北原 邦紀 島根大学, 総合理工学部, 教授 (60304250)
菅原 文彦 東北学院大学, 工学部, 准教授 (70171139)
鈴木 仁志 東北学院大学, 工学部, 講師 (70351319)
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| Co-Investigator(Renkei-kenkyūsha) |
KITAHARA Kuninori 島根大学, 総合理工学部, 教授 (60304250)
SUGAWARA Fumihiko 東北学院大学, 工学部, 准教授 (70171139)
SUZUKI Hitoshi 東北学院大学, 工学部, 准教授 (70351319)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥19,240,000 (Direct Cost: ¥14,800,000、Indirect Cost: ¥4,440,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2007: ¥16,120,000 (Direct Cost: ¥12,400,000、Indirect Cost: ¥3,720,000)
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| Keywords | 多結晶シリコン / 水素化微結晶シリコン / 薄膜トランジスタ / ダブルゲート / TFT / poly-Si / 3次元集積回路 / シリコン / 立体ゲート |
|---|
| Research Abstract |
Self-aligned top and bottom metal double-gate n- and p-chlow-temperature polycrystalline-silicon (poly-Si) thin-film transistors (TFTs) were fabricated on a glass substrate at 550℃. The nominal field-effect mobility of the n- and p-ch TFTs was 635cm^2/Vs and 150cm^2/Vs, respectively, and the s-value of both TFTs was 130mV/dec. The performance characteristics can be used to realize low-power and high-speed circuits on a glass substrate. In order to achieve monolithic 3D integration of TFTs, low-temperature TFT fabrication are necessary for the second and third TFT layers. For this purpose, we developed self-aligned laser-activation top-gate hydrogenated microcrystalline silicon (μc-Si : H) TFTs at a process temperature of 325℃ and achieved a field-effect mobility of 1.1cm^2/Vs in the linear region for n-channel TFTs.
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