Research of residue arithmetic and number conversion circuits using redundant number representation

• Project/Area Number: 19500039
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Gunma University
• Principal Investigator: WEI Shugang Gunma University, 大学院・工学研究科, 教授 (10251125)
• Project Period (FY): 2007 – 2008
• Project Status: Completed (Fiscal Year 2008)
• Budget Amount: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000); Fiscal Year 2008: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000); Fiscal Year 2007: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
• Keywords: 算術演算 / 剰余数系 / 剰余数演算 / 剰余数系-重み数系変換 / SD数表現 / 剰余数-2進数の相互変換 / 剰余乗算逆数 / そろばん演算

Research Abstract

2進SD数表現を用いた剰余数系から従来の2進数系への変更を高速に実行できるハードウェアアルゴリズムを提案した。この方法では、SD数演算の並列処理特徴を生かした。変換に必要な演算をさらに高速に行うため、基本演算回路であるSD数加算回路の高速化方法を考案した。変換回路および算術演算の回路設計およびシミュレーションを行い、高速な回路が得られることを明らかにした。また、そろばん数表現を剰余数系の演算に適用し、高性能の剰余回路の実現が期待できることを設計と回路評価により確認した。

Research Products

• [Journal Article] 算盤アーキテクチャを用いた10進加算器とその剰余演算への応用 (2009)
  • Author(s): 飯島唯仁、魏書剛
  • Journal Title: 電子情報通信学会技術研究報告 DC2008 Pages: 19-23
  • NAID: 110007131394
  • Peer Reviewed
• [Journal Article] Modular Multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation (2009)
  • Author(s): S.Wei
  • Journal Title: Lectures Notes in Engineering and Computer Science Vol.1 Pages: 494-499
  • Peer Reviewed
• [Journal Article] Modular Multipliers Using a Modified Residue Addition Algorithm with Signed-Digit Number Representation (2009)
  • Author(s): S. Wei
  • Journal Title: Lectures Notes in Engineering and Computer Science 1 Pages: 494-499
  • Peer Reviewed
• [Journal Article] 算盤アーキテクチャに基づく算術演算回路 (2008)
  • Author(s): 長澤俊介、魏書剛
  • Journal Title: 電子情報通信学会技術究報告 ICD2007-148 Pages: 53-58
  • NAID: 110006623189
• [Journal Article] A New Residue Adder with Redundant Binary Number Representation (2008)
  • Author(s): S.Wei
  • Journal Title: Proceedings of the 6^<th> Annual IEEE Northeast Workshop on Circuits and Systems Vol.1 Pages: 157-160
  • Peer Reviewed
• [Journal Article] A New Residue Adder with Redundant Binary Number Representation (2008)
  • Author(s): S. Wei
  • Journal Title: Proceedings of the 6th Annual IEEE Northeast Workshop on Circuits and Systems 1 Pages: 157-160
  • Peer Reviewed
• [Journal Article] A fast algorithm for RNS-to-binary conversion (2007)
  • Author(s): S. Chen and S. Wei
  • Journal Title: WSEAS Transactions on Computers Vol. 6 Pages: 733-740
  • Peer Reviewed
• [Journal Article] A multiplicative inverse algorithm based on modulo (2^p -1) signed-digit arithmetic for residue to weighted number conversion (2007)
  • Author(s): S. Wei
  • Journal Title: Proceedings of 2007 IEEE international Symposium on integrated Circuits Vol.1 Pages: 25-28
  • Peer Reviewed
• [Journal Article] A fast algorithm for RNS-to-binary conversion (2007)
  • Author(s): S. Chen and S. Wei
  • Journal Title: WSEAS Transactions on Computers Vol.6 Pages: 733-740
  • Peer Reviewed
• [Journal Article] A multiplicative inverse algorithm based on modulo (2^p-1) siglled・digit arithnetic for residue to weighted number collversion (2007)
  • Author(s): S. Wei
  • Journal Title: Proceedings of 2007 IEEE international Symposium on integrated Circuits Vol.1 Pages: 25-28
  • Peer Reviewed
• [Journal Article] 算盤アーキテクチャに基づく算術演算回路 (2007)
  • Author(s): 長澤 俊介, 魏 書剛
  • Journal Title: 電子情報通信学会技術研究報告 ICD2007-148 Pages: 53-58
  • NAID: 110006623189