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Study on Model Checking for High-Level Hardware Design Descriptions

Research Project

Project/Area Number 19500043
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionOsaka University

Principal Investigator

HAMAGUCHI Kiyoharu  Osaka University, 大学院・情報科学研究科, 准教授 (80238055)

Project Period (FY) 2007 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2007: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Keywords設計検証 / フォーマル検証 / 第1階述語論理 / モデル検査 / 高位ハードウェア設計 / 第一階述語論理 / 高位ハードウェア検証
Research Abstract

Model checking is a technology for verifying the correctness of hardware or software designs, which has been widely used. Designs including complex arithmetic operations are hard to handle even for small designs. In this study, in particular, for high-level design descriptions, an approach that combines multiple logics has been developed and implemented, to abstract away unnecessary details. As a result, some digital signal processing designs have become tractable in term of model checking.

Report

(4 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • 2007 Annual Research Report
  • Research Products

    (11 results)

All 2011 2010 2009 2008 2007

All Journal Article (5 results) (of which Peer Reviewed: 5 results) Presentation (6 results)

  • [Journal Article] Approximate Model Checking using a Subset of First-Order Logic2011

    • Author(s)
      Kiyoharu Hamaguchi, Kazuya Masuda, Toshinobu Kashiwabara
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 5(In printing)

    • NAID

      130000418475

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2010

    • Author(s)
      Hiroaki Shimizu, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 4

      Pages: 105-117

    • NAID

      110009599081

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2010

    • Author(s)
      Hiroaki Shimizu
    • Journal Title

      IPSJ Transactions on System LSI Design Methodology 4

      Pages: 105-117

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2008

    • Author(s)
      Hiroaki Shimizu
    • Journal Title

      Proc. of 6th International Conference on Automated Technology for Verification and Analysis (Lecture Notes in Computer Science) 5311

      Pages: 318-331

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Satisfiability Checking for Logic with Equality and Uninterpreted Functions under Equivalence Constraints2007

    • Author(s)
      Hiroaki Kozawa, Kiyoharu Hamaguchi, Toshinobu Kashiwabara
    • Journal Title

      IEICE Trans. on Fundamentals of Electronics, Communications and Computer Sciences E90-A

      Pages: 2778-2789

    • NAID

      110007538024

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Presentation] 第一階述語論理のサブクラスに対する近似的モデル検査アルゴリズム2009

    • Author(s)
      増田和也
    • Organizer
      第142回システムLSI設計技術研究会
    • Place of Presentation
      高知市文化プラザ (高知)
    • Year and Date
      2009-12-02
    • Related Report
      2009 Annual Research Report
  • [Presentation] SMTソルバーを利用した近似的な非有界モデル検査アルゴリズムにおける複数の論理体系の組み合わせ手法2009

    • Author(s)
      浜口清治
    • Organizer
      組み込みシステムシンポジウム2009
    • Place of Presentation
      国立オリンピック記念青少年総合センター (東京)
    • Year and Date
      2009-10-22
    • Related Report
      2009 Annual Research Report
  • [Presentation] 第一階述語論理のサブクラスに対する近似的モデル検査アルゴリズム2009

    • Author(s)
      増田和也, 浜口清治, 柏原敏伸
    • Organizer
      情報処理学会研究報告
    • Related Report
      2009 Final Research Report
  • [Presentation] SMTソルバーを利用した近似的な非有界モデル検査アルゴリズムにおける複数の論理体系の組み合わせ手法2009

    • Author(s)
      浜口清治
    • Organizer
      組み込みシステムシンポジウム2009論文集
    • Related Report
      2009 Final Research Report
  • [Presentation] Toshinobu Kashiwabara Approximate Invariant Property Checking Using Term-Height Reduction for a Subset of First-Order Logic2008

    • Author(s)
      Hiroaki Shimizu, Kiyoharu Hamaguchi
    • Organizer
      6th International Conference on Automated Technology for Verification and Analysis
    • Place of Presentation
      LNCS
    • Related Report
      2009 Final Research Report
  • [Presentation] 第一階述語論理のサブクラスに対する項の高さ縮減を用いた不変条件の近似的検証アルゴリズム2007

    • Author(s)
      清水博章, 浜口清治, 柏原敏伸
    • Organizer
      情報処理学会研究報告
    • Related Report
      2009 Final Research Report

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Published: 2007-04-01   Modified: 2016-04-21  

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