| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2007: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Research Abstract |
This research addressed the false test issues in at-speed scan testing of LSI circuits. First, it identified the excessive switching activity in the proximity (critical area) around a long sensitized path by a test vector as the main cause of false test. Next, it proposed an accurate metric for identifying risky test vectors by taking the sensitization status of long sensitized paths, proximity information, and transition level into consideration. Furthermore, this research proposed a method for extracting redundant bits from a test set that can impact the switching activity in critical areas and devised an X-filling method for determining logic values for the redundant bits so that switching activity in critical areas is effectively reduced. As a result, an advanced false-test-avoiding scheme has been established.
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