Research on Advanced VLSI Test for Avoiding Signal Degradation
Project/Area Number |
19500047
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Research Category |
Grant-in-Aid for Scientific Research (C)
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Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
Computer system/Network
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Research Institution | Kyushu Institute of Technology |
Principal Investigator |
WEN Xiaoqing Kyushu Institute of Technology, 大学院・情報工学研究院, 教授 (20250897)
|
Co-Investigator(Kenkyū-buntansha) |
KAJIHARA Seiji 九州工業大学, 大学院・情報工学研究院, 教授 (80252592)
|
Project Period (FY) |
2007 – 2009
|
Project Status |
Completed (Fiscal Year 2009)
|
Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2007: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
|
Keywords | LSIテスト / 高信頼化 |
Research Abstract |
This research addressed the false test issues in at-speed scan testing of LSI circuits. First, it identified the excessive switching activity in the proximity (critical area) around a long sensitized path by a test vector as the main cause of false test. Next, it proposed an accurate metric for identifying risky test vectors by taking the sensitization status of long sensitized paths, proximity information, and transition level into consideration. Furthermore, this research proposed a method for extracting redundant bits from a test set that can impact the switching activity in critical areas and devised an X-filling method for determining logic values for the redundant bits so that switching activity in critical areas is effectively reduced. As a result, an advanced false-test-avoiding scheme has been established.
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Report
(4 results)
Research Products
(58 results)
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[Presentation] A Capture-Safe Test Generation Scheme for At-Speed Scan Testing2008
Author(s)
X. Wen, K. Miyase, S. Rajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. It o, K. Hatayama, T. Aikyo, K. K. Saluia
Organizer
IEEE European Test Symposium
Place of Presentation
Verbania, Italy
Year and Date
2008-05-26
Related Report
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[Presentation] A Capture- Safe Test Generation Scheme for At-Speed Scan Testing2008
Author(s)
X. Wen, K. Miyase, S. Kajihara, H. Furukawa, Y. Yamato, A. Takashima, K. Noda, H. Ito, K. Hatayama, T. Aikyo, K.K. Saluja
Organizer
Proc. IEEE European Test Symp.
Related Report
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