| Project/Area Number |
19500048
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Hiroshima City University |
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Principal Investigator |
INOUE Tomoo Hiroshima City University, 情報科学研究科, 教授 (40252829)
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| Co-Investigator(Kenkyū-buntansha) |
市原 英行 広島市立大学, 情報科学研究科, 准教授 (50326427)
吉川 祐樹 広島市立大学, 情報科学研究科, 助教 (50453212)
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| Co-Investigator(Renkei-kenkyūsha) |
ICHIHARA Hideyuki 広島市立大学, 情報科学研究科, 准教授 (50326427)
YOSHIKAWA Yuki 広島市立大学, 情報科学研究科, 助教 (50453212)
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| Project Period (FY) |
2007 – 2009
|
| Project Status |
Completed (Fiscal Year 2009)
|
| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2007: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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| Keywords | 設計自動化 / テスト容易化設計 / VLSI-CAD / システムオンチップ.ディペンダブル・コンピューティング / テスト生成 / システムオンチップ / ディペンダブル・コンピューティング |
|---|
| Research Abstract |
This work proposed a class of partial thru testable sequential circuits.
The class is a sub-class of acyclically sequential ones, and properly includes a class of full thru testable sequential ones. This work also proposed an efficient method for generating test sets for partial thru sequential circuits, and an algorithm for designing partial thrutestable sequential circuits. The result of this work contributes to the reduction in hardware overhead for testability compared with the conventional full scan design with keeping complete fault efficiency.
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