| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2009: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2008: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2007: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Research Abstract |
We have achieved the followings for time-domain analog circuit technology in nano CMOS VLSI:
(1) High-speed, low-power AD converter architecture using time-domain redundancy algorithm.
(2) Two novel time-to-digital converter architectures
2-1) Stochastic time-to-digital converter with self-calibration
2-2) High-resolution, low-power time-to-digital converter by improving the vernia-type architecture.
(3) High-resolution, low-power digital PMW generator architecture and its application to digitally-controlled power supply
(4) EMI reduction spread-spectrum clocking algorithm with combination of PWM and PPM (pulse position modulation) in digitally-controlled power supply.
(5) Development of all digital phase-clocked loop circuit for TV tuner application with fast frequency locking.
(6) Low-noise high-frequency waveform sampling method.These results have been transferred to industry through patents and papers.
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