Development of a sensor-node processor with four order of magnitude variable power dissipation
Project/Area Number |
19680002
|
Research Category |
Grant-in-Aid for Young Scientists (A)
|
Allocation Type | Single-year Grants |
Research Field |
Computer system/Network
|
Research Institution | Osaka University |
Principal Investigator |
HASHIMOTO Masanori Osaka University, 大学院・情報科学研究科, 准教授 (80335207)
|
Project Period (FY) |
2007 – 2009
|
Project Status |
Completed (Fiscal Year 2009)
|
Budget Amount *help |
¥22,490,000 (Direct Cost: ¥17,300,000、Indirect Cost: ¥5,190,000)
Fiscal Year 2009: ¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000)
Fiscal Year 2008: ¥8,970,000 (Direct Cost: ¥6,900,000、Indirect Cost: ¥2,070,000)
Fiscal Year 2007: ¥8,320,000 (Direct Cost: ¥6,400,000、Indirect Cost: ¥1,920,000)
|
Keywords | ハードウェア設計 / センサネットワーク / サブスレッショルド回路 / 超低消費電力 / 製造ばらつき / 性能補償 / 基板バイアス / 動的タイミング変動 / プロセッサ / レイアウト方式 |
Research Abstract |
This project developed a processor that realizes "ultra-low power operation" demanded to sensor nodes composing sensor networks. Also, device modeling and circuit techniques needed to implement the processor was developed. Evaluating the processor on a test chip fabricated in 65nm process, the processor archived 4.18pJ/cycle at 0.5V in a normal synchronized operation mode, and the energy dissipation was further reduced by introducing an asynchronous operation.
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Report
(4 results)
Research Products
(30 results)