Development of a sensor-node processor with four order of magnitude variable power dissipation

• Project/Area Number: 19680002
• Research Category: Grant-in-Aid for Young Scientists (A)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Osaka University
• Principal Investigator: HASHIMOTO Masanori Osaka University, 大学院・情報科学研究科, 准教授 (80335207)
• Project Period (FY): 2007 – 2009
• Project Status: Completed (Fiscal Year 2009)
• Budget Amount: ¥22,490,000 (Direct Cost: ¥17,300,000、Indirect Cost: ¥5,190,000); Fiscal Year 2009: ¥5,200,000 (Direct Cost: ¥4,000,000、Indirect Cost: ¥1,200,000); Fiscal Year 2008: ¥8,970,000 (Direct Cost: ¥6,900,000、Indirect Cost: ¥2,070,000); Fiscal Year 2007: ¥8,320,000 (Direct Cost: ¥6,400,000、Indirect Cost: ¥1,920,000)
• Keywords: ハードウェア設計 / センサネットワーク / サブスレッショルド回路 / 超低消費電力 / 製造ばらつき / 性能補償 / 基板バイアス / 動的タイミング変動 / プロセッサ / レイアウト方式

Research Abstract

This project developed a processor that realizes "ultra-low power operation" demanded to sensor nodes composing sensor networks. Also, device modeling and circuit techniques needed to implement the processor was developed. Evaluating the processor on a test chip fabricated in 65nm process, the processor archived 4.18pJ/cycle at 0.5V in a normal synchronized operation mode, and the energy dissipation was further reduced by introducing an asynchronous operation.

Research Products

• [Journal Article] Alpha-Particle-Induced Soft Errors and Multiple Cell Upsets in 65-nm 10T Subthreshold SRAM (2010)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of International Reliability Physics Symposium (IRPS) Pages: 213-217
  • Peer Reviewed
• [Journal Article] A 16-Bit RISC Processor with 4. 18pJ/cycle at 0. 5V Operation (2010)
  • Author(s): D. Kuroda, H. Fuketa, M. Hashimoto, T. Onoye
  • Journal Title: Proceedings of IEEE COOL Chips Pages: 190-190
  • Peer Reviewed
• [Journal Article] Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits (2010)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Pages: 361-362
  • Peer Reviewed
• [Journal Article] Adaptive Performance Control with Embedded Timing Error Predictive Sensors for Subthreshold Circuits (2010)
  • Author(s): H.Fuketa, M.Hashimoto, Y.Mitsuyama, T.Onoye
  • Journal Title: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Pages: 361-362
  • Peer Reviewed
• [Journal Article] Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction (2009)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: IEICE Trans. on Fundamentals vol.E92-A,no.12 Pages: 3094-3102
  • NAID: 10026861488
  • Peer Reviewed
• [Journal Article] Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits (2009)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of IEEE Custom Integrated Circuits Conference (CICC) Pages: 215-218
  • Peer Reviewed
• [Journal Article] Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits (2009)
  • Author(s): K. Hamamoto, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pages: 51-56
  • Peer Reviewed
• [Journal Article] Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction (2009)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of Asia and South Pacific Design Automation Conference (ASP-DAC) Pages: 266-271
  • NAID: 10026861488
  • Peer Reviewed
• [Journal Article] Trade-off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction (2009)
  • Author(s): H.Fuketa, M.Hashimoto, Y.Mitsuyama, T.Onoye
  • Journal Title: IEICE Trans.on Fundamentals Vol.E92-A,No.12 Pages: 3094-3102
  • NAID: 10026861488
  • Peer Reviewed
• [Journal Article] Adaptive Performance Compensation with In-Situ Timing Error Prediction for Subthreshold Circuits (2009)
  • Author(s): H.Fuketa, M.Hashimoto, Y.Mitsuyama, T.Onoye
  • Journal Title: Proceedings of IEEE Custom Integrated Circuits Conference (CICC) Pages: 215-218
  • Peer Reviewed
• [Journal Article] Tuning-Friendly Body Bias Clustering for Compensating Random Variability in Subthreshold Circuits (2009)
  • Author(s): K.Hamamoto, M.Hashimoto, Y.Mitsuyama, T.Onoye
  • Journal Title: Proc.of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pages: 51-56
  • Peer Reviewed
• [Journal Article] An Experimental Study on Body-Biasing Layout Style Focusing on Area Efficiency and Speed Controllability (2009)
  • Author(s): K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: IEICE Trans. on Electronics vol.E92-no.2 Pages: 281-285
  • NAID: 10026821218
  • Peer Reviewed
• [Journal Article] Trade-Off Analysis between Timing Error Rate and Power Dissipation for Adaptive Speed Control with Timing Error Prediction (2009)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, and T. Onoye
  • Journal Title: Proceedings of Asia and South Pacific Design Automation Conference(ASP-DAC) Pages: 266-271
  • NAID: 10026861488
  • Peer Reviewed
• [Journal Article] Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits (2008)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of IEEE/ACM International Symposium on Low Power Electronics and Design (ISLPED) Pages: 3-8
  • Peer Reviewed
• [Journal Article] Correlation Verification between Transistor Variability Model with Body Biasing and Ring Oscillation Frequency in 90nm Subthreshold Circuits (2008)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proc. IEEE/ACM International Symposium on Low Power Electronics and Design(ISLPED) Pages: 3-8
  • Peer Reviewed
• [Journal Article] Experimental Study on Body-Biasing Layout Style--Negligible Area Overhead Enables Sufficient Speed Controllability-- (2008)
  • Author(s): K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyanma, T. Onoye
  • Journal Title: Proc. ACM Great Lake Symposium on VLSI(GLSVLSI) Pages: 387-390
  • Peer Reviewed
• [Journal Article] Experimental Study on Body-Biasing Layout Style - Negligible Area Overhead Enables Suffcient Speed Controllability - (2008)
  • Author(s): K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of ACM Great Lake Symposium on vLSI (GLSVLSI)
  • Peer Reviewed
• [Journal Article] A study on body-biasing layout style focusing on area efficiency and speed (2007)
  • Author(s): K. Hamamoto, H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: Proceedings of Workshop on Synthesis and System Integration of Mixed Technologies (SASIMI) Pages: 233-237
  • Peer Reviewed
• [Journal Article] Transistor Variability Modeling and Its Validation with Ring-Oscillation Frequencies for Body-Biased Subthreshold Circuits
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Journal Title: IEEE Trans. on VLSI Systems (in press)
  • Peer Reviewed
• [Presentation] 製造ばらつきや環境変動を許容するサブスレッショルド回路設計 (2010)
  • Author(s): 橋本昌宜, 更田裕司, 尾上孝雄
  • Organizer: 2010年電子情報通信学会総合大会
  • Place of Presentation: 仙台市
  • Year and Date: 2010-03-17
• [Presentation] 製造ばらつきや環境変動を許容するサブスレッショルド回路設計 (2010)
  • Author(s): 橋本昌宜, 更田裕司, 尾上孝雄
  • Organizer: 2010年電子情報通信学会総合大会
  • Place of Presentation: 宮城県仙台市・於東北大学
  • Year and Date: 2010-03-17
• [Presentation] Robust Subthreshold Circuit Design to Manufacturing and Environmental Variability (2010)
  • Author(s): M.Hashimoto
  • Organizer: NTU-Waseda Joint Workshop 2010
  • Place of Presentation: 台湾台北市・於Taipei International Converntion Center
  • Year and Date: 2010-01-22
• [Presentation] 低消費エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価 (2009)
  • Author(s): 黒田弾, 更田裕司, 橋本昌宜, 尾上孝雄
  • Organizer: 情報処理学会SLDM研究会
  • Place of Presentation: 金沢市
  • Year and Date: 2009-10-16
• [Presentation] 低消費エネルギー動作に適した超低電圧プロセッサのアーキテクチャ評価 (2009)
  • Author(s): 黒田弾, 更田裕司, 橋本昌宜, 尾上孝雄
  • Organizer: 情報処理学会SLDM研究会
  • Place of Presentation: 福井県あわら市・於まつや千千
  • Year and Date: 2009-10-16
• [Presentation] レイアウトを考慮した基板バイアスクラスタリング手法 (2009)
  • Author(s): 濱本浩一, 橋本昌宜, 密山幸男, 尾上孝雄
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 那覇市
  • Year and Date: 2009-03-13
• [Presentation] サブスレッショルド回路における基板バイアスを考慮したトランジスタのばらつきモデリングとリングオシレータを用いた検証 (2009)
  • Author(s): 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 那覇市
  • Year and Date: 2009-03-13
• [Presentation] Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-Biased Circuits and Subthreshold Circuits (2008)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuyama, T. Onoye
  • Organizer: Proceedings of Workshop on Test Structure Design for Variability Characterization
  • Place of Presentation: San Jose (USA)
  • Year and Date: 2008-11-13
• [Presentation] Vth Variation Modeling and Its Validation with Ring Oscillation Frequencies for Body-biased Circuits and Subthreshold Circuits (2008)
  • Author(s): H. Fuketa, M. Hashimoto, Y. Mitsuvama, T. Onoye
  • Organizer: Workshop on Test Structure Design for Variability Characterization
  • Place of Presentation: アメリカ合衆国サンノゼ
  • Year and Date: 2008-11-13
• [Presentation] タイミングエラー予告を用いた適応的速度制御におけるタイミングエラー頻度と消費電力のトレードオフ解析 (2008)
  • Author(s): 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
  • Organizer: 情報処理学会DAシンポジウム
  • Place of Presentation: 浜松市
  • Year and Date: 2008-08-27
• [Presentation] 基板バイアス印加レイアウト方式の面積効率と速度制御性の評価 (2008)
  • Author(s): 濱本浩一, 更田裕司, 橋本昌宜, 密山幸男, 尾上孝雄
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 札幌市
  • Year and Date: 2008-06-26