Automatic False Path Identification and Test Synthesis System Development to Avoid Overtesting
| Project/Area Number |
19700045
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Waseda University |
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Principal Investigator |
SHI Youhua Waseda University, IT研究機構, 講師 (70409655)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥3,770,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥570,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2007: ¥1,300,000 (Direct Cost: ¥1,300,000)
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| Keywords | 設計自動化 / 回路とシステム / VLSI設計技術 / 回路設計・CAD / 設計自動化システム / フォールスパス解析 / システムLSIテスト / テスト設計 / テストアーキテクチャ / タイミング解析 / 合成システム / 過剰テスト |
|---|
| Research Abstract |
The progress of design and manufacturing technology of LSIs makes it possible to realize more functional blocks into a chip with high speed and low power consumption. However it also leads to many new design challenges and one of them is the design and test technique due to the existence of false paths in the designs. Therefore in this research, a new analysis and test synthesis system was developed for the low cost design and test of next-generation LSIs, and with the use of this system novel test techniques, more specifically response compaction techniques and non-overtesting delay test methods, were developed.
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Report
(4 results)
Research Products
(16 results)
