Design and Implementation of Fast Digital Filters with the Shift Operation Circuits and Single Multiplier
| Project/Area Number |
19760289
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Control engineering
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| Research Institution | Hiroshima University |
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Principal Investigator |
FUKUMITSU Masayoshi Hiroshima University, 大学院・工学研究科, 助教 (00403585)
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| Project Period (FY) |
2007 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥2,790,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥390,000)
Fiscal Year 2009: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2008: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2007: ¥1,100,000 (Direct Cost: ¥1,100,000)
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| Keywords | ディジタルフィルタ / 分枝限定法 / フィルタ設計 / 共有乗算器 / シフト演算回路 / 最適化アルゴリズム / 電子透かし / フィノヒタ設計 |
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| Research Abstract |
We have proposed a design algorithm for the finite wordlength digital filters based on the lower bound estimation using the Lagrange multiplier method. Next, we have applied this method to the error feedback network which is useful for the reduction of product roundoff noise of digital filters. Also, we have shown the design algorithm for the FIR digital filters with the shift operation circuits and single multiplier by combining the Lagrange multiplier method and the branch-and-bound method. We have discussed the effectiveness of the above methods based on the result of computer simulation. We have considered the digital watermarking as the application of the digital filters.
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Report
(4 results)
Research Products
(18 results)
