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Design and Implementation of Fast Digital Filters with the Shift Operation Circuits and Single Multiplier

Research Project

Project/Area Number 19760289
Research Category

Grant-in-Aid for Young Scientists (B)

Allocation TypeSingle-year Grants
Research Field Control engineering
Research InstitutionHiroshima University

Principal Investigator

FUKUMITSU Masayoshi  Hiroshima University, 大学院・工学研究科, 助教 (00403585)

Project Period (FY) 2007 – 2009
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥2,790,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥390,000)
Fiscal Year 2009: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2008: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2007: ¥1,100,000 (Direct Cost: ¥1,100,000)
Keywordsディジタルフィルタ / 分枝限定法 / フィルタ設計 / 共有乗算器 / シフト演算回路 / 最適化アルゴリズム / 電子透かし / フィノヒタ設計
Research Abstract

We have proposed a design algorithm for the finite wordlength digital filters based on the lower bound estimation using the Lagrange multiplier method. Next, we have applied this method to the error feedback network which is useful for the reduction of product roundoff noise of digital filters. Also, we have shown the design algorithm for the FIR digital filters with the shift operation circuits and single multiplier by combining the Lagrange multiplier method and the branch-and-bound method. We have discussed the effectiveness of the above methods based on the result of computer simulation. We have considered the digital watermarking as the application of the digital filters.

Report

(4 results)
  • 2009 Annual Research Report   Final Research Report ( PDF )
  • 2008 Annual Research Report
  • 2007 Annual Research Report
  • Research Products

    (18 results)

All 2010 2009 2008 2007 Other

All Journal Article (12 results) (of which Peer Reviewed: 12 results) Presentation (4 results) Remarks (2 results)

  • [Journal Article] Fast Arithmetic Error Feedback Circuits for Digital Filters with Shift Operation Circuits and Shared Multiplier2010

    • Author(s)
      M.Nakamoto
    • Journal Title

      Proc. of The 53th IEEE International Midwest Symposium on Circuits & Systems ((採録済))

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] M. Nakamoto, T. Hinamoto and S. Ohno Branch and Bound Method for FIR Digital Filters Design with the Shift Operation Circuits and Single Multiplier2009

    • Author(s)
      M. Nakamoto, T. Hinamoto, S. Ohno
    • Journal Title

      Proc. of The 24th International Technical Conference on Circuits/Systems, Computers and Communications

      Pages: 192-195

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] Branch and Bound Method for FIR Digital Filters Design with the Shift Operation Circuits and Single Multiplier2009

    • Author(s)
      M.Nakamoto
    • Journal Title

      Proc. of The 24th International Technical Conference on Circuits/Systems, Computers and Communications

      Pages: 492-495

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design for IIR Digital Filters with Discrete Coefficients Using Weighted Modified Least-Square Criterion2008

    • Author(s)
      M. Nakamoto, Y. Hayakawa, Y. Kurumaj, T. Hinamoto
    • Journal Title

      Proc. of The 23rd International Technical Conference on Circuits/Systems, Computers and Communications

      Pages: 1049-1052

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] 重み付き修正最小2乗法を用いた有限語長ディジタルフィルタの設計2008

    • Author(s)
      中本昌由, 早川裕貴, 車地豊, 雛元孝夫
    • Journal Title

      第21回回路とシステム(軽井沢)ワークショップ講演論文集

      Pages: 143-146

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] 重み付き修正最小2乗法を用いた有限語長ディジタルフィルタの設計2008

    • Author(s)
      中本昌由
    • Journal Title

      第21回回路とシステム(軽井沢)ワークショップ講演論文集

      Pages: 143-146

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Design for IIR Digital Filters with Discrete Coefficients Using Weighted Modified Least-Square Criterion2008

    • Author(s)
      M. Nakamoto
    • Journal Title

      Proc. The 23rd International Technical, Conference on Circuits/Systems, Computers and Communications

      Pages: 1049-1052

    • Related Report
      2008 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Finite Wordlength Design for IIR Digital Filters based on the Modified Least-Square Criterion in the Frequency Domain2007

    • Author(s)
      M. Nakamoto, T. Yoshiya, T. Hinamoto
    • Journal Title

      Proc. of 2007 International Symposium on Intelligent Signal Processing and Communication Systems

      Pages: 25-28

    • NAID

      10018436815

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] ビットパターン埋込み可能な画像電子透かし法に対する新しい鍵系列の提案2007

    • Author(s)
      中本昌由, 藤本卓, 土井章充, 雛元孝夫
    • Journal Title

      第20回回路とシステム(軽井沢)ワークショップ講演論文集

      Pages: 619-624

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Journal Article] ビットパターン埋込み可能な画像電子透かし法に対する新しい鍵系列の提案2007

    • Author(s)
      中本昌由
    • Journal Title

      第19回回路とシステム(軽井沢)ワークショップ講演論文集 11

      Pages: 619-624

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Finite Wordlengfth Design for IIR Digital Filters based on the Modified Least-Square Criterion in the Frequency Domain2007

    • Author(s)
      M. Nakamoto
    • Journal Title

      Proc. of 2007 International Sjanposium on InteUig

      Pages: 25-28

    • Related Report
      2007 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Fast Arithmetic Error Feedback Circuits for Digital Filters with Shift Operation Circuits and Shared Multiplier

    • Author(s)
      M. Nakamoto, T. Hinamoto, S. Ohno
    • Journal Title

      Proc. of The 53th IEEE International Midwest Symposium on Circuits & Systems (採録済)

    • Related Report
      2009 Final Research Report
    • Peer Reviewed
  • [Presentation] ディジタルフィルタを用いた相関利用型画像電子透かし法2009

    • Author(s)
      中本昌由, 門田英晃, 大野修一
    • Organizer
      電気・情報関連学会中国支部第60回連合大会講演論文集
    • Place of Presentation
      広島市立大学
    • Year and Date
      2009-10-17
    • Related Report
      2009 Annual Research Report 2009 Final Research Report
  • [Presentation] 分枝限定法を用いた有限語長ディジタルフィルタの重み付き修正最小2乗設計2008

    • Author(s)
      中本昌由, 早川裕貴, 車地豊, 雛元孝夫
    • Organizer
      電気・情報関連学会中国支部第59回連合大会講演論文集
    • Place of Presentation
      鳥取大学
    • Year and Date
      2008-10-25
    • Related Report
      2009 Final Research Report 2008 Annual Research Report
  • [Presentation] GAによるDWT利用型画像電子透かし法における鍵の最適化2007

    • Author(s)
      中本昌由, 藤本卓, 土井章充, 雛元孝夫
    • Organizer
      電気・情報関連学会中国支部第58回連合大会講演論文集
    • Place of Presentation
      広島大学
    • Year and Date
      2007-10-20
    • Related Report
      2009 Final Research Report
  • [Presentation] GAによるDWT利用型画像電子透かし法における鍵の最適化2007

    • Author(s)
      中本昌由
    • Organizer
      電気・情報関連学会中国支部第57回連合大会演論文集
    • Place of Presentation
      広島大学
    • Year and Date
      2007-10-20
    • Related Report
      2007 Annual Research Report
  • [Remarks] 2008年10月に発表した分枝限定法を用いた有限語長ディジタルフィルタの設計に関する研究成果が平成20年度電気学会論文発表賞に選定された.

    • Related Report
      2009 Final Research Report
  • [Remarks] 平成20年度電気学会論文発表賞発表者中本昌由題目「分枝限定法を用いた有限語長ディジタルフィルタの重み付き修正最小2乗設計」

    • Related Report
      2009 Final Research Report

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Published: 2007-04-01   Modified: 2016-04-21  

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