2D tunnel FET based on understanding of 2D hetero interface characteristics
Project/Area Number |
19H00755
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Research Category |
Grant-in-Aid for Scientific Research (A)
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Allocation Type | Single-year Grants |
Section | 一般 |
Review Section |
Medium-sized Section 21:Electrical and electronic engineering and related fields
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Research Institution | The University of Tokyo |
Principal Investigator |
Kosuke NAGASHIO 東京大学, 大学院工学系研究科(工学部), 教授 (20373441)
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Co-Investigator(Kenkyū-buntansha) |
吾郷 浩樹 九州大学, グローバルイノベーションセンター, 教授 (10356355)
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Project Period (FY) |
2019-04-01 – 2022-03-31
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Project Status |
Completed (Fiscal Year 2021)
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Budget Amount *help |
¥45,500,000 (Direct Cost: ¥35,000,000、Indirect Cost: ¥10,500,000)
Fiscal Year 2021: ¥6,110,000 (Direct Cost: ¥4,700,000、Indirect Cost: ¥1,410,000)
Fiscal Year 2020: ¥21,970,000 (Direct Cost: ¥16,900,000、Indirect Cost: ¥5,070,000)
Fiscal Year 2019: ¥17,420,000 (Direct Cost: ¥13,400,000、Indirect Cost: ¥4,020,000)
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Keywords | 超低消費電力 / トンネル現象 / 電界効果トランジスタ / 2次元材料 / 超低消費電力デバイス / トンネルトランジスタ / トンネルFET / 2次元層状材料 / ヘテロ界面 / 低消費電力 / 2Dヘテロ界面 / MoS2 / WSe2 / h-BN |
Outline of Research at the Start |
IoTデバイスの数は,数年後には~400億個に達すると指摘されており,低消費電力化が期待できる3次元系のトンネルFETが研究されているが,オン電流が低いという問題がある.原子レベルで急峻かつ電気的に不活性である2D-2Dヘテロ界面をトンネルFETに適応することで,トンネル距離を理想的には層間距離であるvan der Waals距離にまで低減できると考えられ,オン電流向上へのブレークスルーとなる可能性がある.本研究課題は,低消費電力デバイスとして期待がかかるトンネルFETに2次元層状物質の原子レベルで急峻かつ電気的に不活性な界面を適応することでさらなる低消費電力化を目指すものである.
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Outline of Final Research Achievements |
Two-dimensional tunnel FETs (2D-TFETs) that can realize high drive current by reducing the tunnel distance to van der Waals distance as well as low power consumption have been intensively studied. In this study, we investigated high concentration N-type two-dimensional crystals aiming at complementary operation and found that SnS2 is suitable as a high-concentration N-type crystal for TFET. Furthermore, a P+MoS2/N-MoS2 heterostructure tunnel FET was fabricated with h-BN gate dielectric. Finally, we achieved SS of 51 mV / dec, which is less than the theoretical limit of 60 mV/dec of MOSFET. This result is high impact to ultra-low power consumption.
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Academic Significance and Societal Importance of the Research Achievements |
IoTデバイス数は,数年後には~400億個に達すると指摘されているが,電子デバイスの超低消費電力化が普及の鍵である.本研究では,従来のSiトランジスタ動作の急峻性を表すSSにおいて理論限界値である60 mV/dec以下の51 mV/decを達成した.本成果は,低消費電力デバイスとして期待がかかる2次元トンネルFETの低消費電力動作を実証したものであり,今後の展開が大いに期待される.
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Report
(5 results)
Research Products
(93 results)
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[Presentation] "Experimental Demonstration of In-Plane Ferroelectricity in SnS Down to Monolayer",2020
Author(s)
N. Higashitarumizu, H. Kawamoto, C.-J. Lee, B.-H. Lin, F.-H. Chu, I. Yonemori, T. Nishimura, K. Wakabayashi, W.-H. Chang, K. Nagashio,t.
Organizer
2020 Virtual MRS Spring/Fall meeting, (Nov./Dec. 2020, online, USA).
Related Report
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[Presentation] "The demonstration of SS below 60 mV/dec at RT in all 2D heterostructure TFET",2020
Author(s)
K. Nakamura, N. Nagamura, K. Ueno, T. Taniguchi, K. Watanabe, Kosuke Nagashio,
Organizer
International Conference on Solid State Devices and Materials (SSDM), (September. 30, 2020, All-VIRTUAL conference).
Related Report
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[Presentation] "Understanding the Tunneling Behavior in 2D Based Floating Gate Type Memory Device by Measuring Floating Gate Voltage",2020
Author(s)
Taro Sasaki, Keiji Ueno, Takashi Taniguchi, Kenji Watanabe, Tomonori Nishimura, Kosuke Nagashio,
Organizer
International Conference on Solid State Devices and ypMaterials (SSDM), (September. 30, 2020, All-VIRTUAL conference).
Related Report
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[Presentation] "Screw dislocation driven spiral growth in SnS initiated by atomic graphene steps",2020
Author(s)
Yih-Ren Chang, Naoki Higashitarumizu, Hayami Kawamoto, Fu-Hsien Chu, Chien-Ju Lee, Tomonori Nishimura, Wen-Hao Chang, Kosuke Nagashio,
Organizer
International Conference on Solid State Devices and Materials (SSDM), (September. 28, 2020, All-VIRTUAL conference).
Related Report
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[Presentation] "Understanding the device operation of ambipolar channel based 2D memory devices by trajectory of floating gate voltage",2020
Author(s)
T. Sasaki, K. Ueno, T. Taniguchi, K. Watanabe, T. Nishimura, and K. Nagashio,
Organizer
78th Device Research Conference, (June 23, 2020, Online).
Related Report
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[Presentation] CVD-2層グラフェンのh-BNヘテロFET動作解析による結晶性評価,2020
Author(s)
西山 航, Solis-Fernandez Pablo, 寺尾 友里, 河原 憲治, 吾郷 浩樹, 西村 知紀, 長汐 晃輔,
Organizer
2020年第81回応用物理学会秋季学術講演会, (2020年9月9日, オンライン開催).
Related Report
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[Presentation] "2D layered semiconductors",2019
Author(s)
K. Nagashio,
Organizer
7th International symposium on organic and inorganic electronic materials and related nanotechnology, (June 19-22, 2019, Shinshu Univ. Nagano, Japan).
Related Report
Int'l Joint Research / Invited
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[Presentation] "Band Alignment in Charge- Transfer-Type p+-WSe2/MoS2 Tunnel FET",2019
Author(s)
K. Nakamura, N. Nagamura, K. Ueno, T. Taniguchi, K. Watanabe, K. Nagashio,
Organizer
International Conference on Solid State Devices and Materials (SSDM), (September. 4, 2019, Nagoya University, Nagoya).
Related Report
Int'l Joint Research
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[Presentation] "PVD growth of monolayer SnS under S-rich condition toward piezoelectric application",2019
Author(s)
H. Kawamoto, N. Higashitarumizu, M. Nakamura, I. Yonemori, K. Wakabayashi, K. Nagashio,
Organizer
International Conference on Solid State Devices and Materials (SSDM), (September. 4, 2019, Nagoya University, Nagoya).
Related Report
Int'l Joint Research
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[Presentation] "Electromechanical Response of Few-to-monolayer SnS PVD-grown on Flexible Mica",2019
Author(s)
N. Higashitarumizu, H. Kawamoto, K. Nagashio,
Organizer
2019 MRS Spring Meeting, (April, 26, 2019, Phoenix Convention Center, Phoenix, USA).
Related Report
Int'l Joint Research
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[Presentation] "Photoresponse in h-BN encapsulated bilayer graphene field-effect phototransistor",2019
Author(s)
Uwanno, T. Taniguchi, K. Watanabe, & K. Nagashio,
Organizer
2019 MRS Spring Meeting, (April, 26, 2019, Phoenix Convention Center, Phoenix, USA).
Related Report
Int'l Joint Research
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