Integration of Image Sensor and Analog CNN Circuits Reducing Image Recognition Energy by Factor of 1/1000
Project/Area Number |
19H02188
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Research Category |
Grant-in-Aid for Scientific Research (B)
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Allocation Type | Single-year Grants |
Section | 一般 |
Review Section |
Basic Section 21060:Electron device and electronic equipment-related
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Research Institution | The University of Tokyo |
Principal Investigator |
|
Project Period (FY) |
2019-04-01 – 2022-03-31
|
Project Status |
Completed (Fiscal Year 2021)
|
Budget Amount *help |
¥16,380,000 (Direct Cost: ¥12,600,000、Indirect Cost: ¥3,780,000)
Fiscal Year 2021: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2020: ¥8,190,000 (Direct Cost: ¥6,300,000、Indirect Cost: ¥1,890,000)
Fiscal Year 2019: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
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Keywords | 画像認識 / 畳み込みニューラルネットワーク / 撮像素子 / エネルギー / 回路 |
Outline of Research at the Start |
AI技術を広く社会に普及させる際の最大の課題が、大消費電力である。特に、深層畳み込みニューラルネットワーク(CNN)を用いた画像認識の消費電力が大きい。そこで、撮像素子の直近にCNN回路を集積化する新技術により、CNN計算のエネルギーを3桁減らすことを目指す。
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Outline of Final Research Achievements |
With the widespread use of AI technology, ultra-low latency convolutional neural network (CNN) processing is highly demanded in fields that require real-time image classification such as autonomous driving and VR applications. This paper proposes an ultra-low-latency all-digital in-imager 2D binary convolutional neural network (II2D-BNN) accelerator for image classification. In II2D-BNN, multiply-accumulate operations (MACs) are processed inside the imager array parallelly in 2D, without extra latency for the row-by-row processing and data access with random access memories (RAMs). Convolution and sub-sampling operations using a 3 × 3 kernel are completed in only nine steps of batch-processing-in-2D regardless of image size using the II2D-BNN architecture, leading to over 88.5% reduction in computing latency compared with state-of-the-art architectures using batch-processing-in-1D.
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Academic Significance and Societal Importance of the Research Achievements |
本研究成果「デジタルIn-Imager二次元畳み込みニューラルネットワークアクセラレータIC」により、将来、深層畳み込みニューラルネットワークを用いた高精度の画像認識を低消費電力かつ低遅延時間に実現可能になることが期待される。
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Report
(4 results)
Research Products
(3 results)