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On a noise convolutional neural network

Research Project

Project/Area Number 19H04078
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Review Section Basic Section 60040:Computer system-related
Research InstitutionTohoku University (2023)
Tokyo Institute of Technology (2019-2022)

Principal Investigator

Nakahara Hiroki  東北大学, 未踏スケールデータアナリティクスセンター, 教授 (20624414)

Co-Investigator(Kenkyū-buntansha) 佐野 健太郎  国立研究開発法人理化学研究所, 計算科学研究センター, チームリーダー (00323048)
佐藤 真平  信州大学, 学術研究院工学系, 准教授 (80782763)
Project Period (FY) 2019-04-01 – 2024-03-31
Project Status Completed (Fiscal Year 2023)
Budget Amount *help
¥17,160,000 (Direct Cost: ¥13,200,000、Indirect Cost: ¥3,960,000)
Fiscal Year 2023: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2022: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2021: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2020: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2019: ¥6,760,000 (Direct Cost: ¥5,200,000、Indirect Cost: ¥1,560,000)
KeywordsAI / Machine learning / FPGA / Machine Learning / ニューラルネットワーク / 雑音畳み込み / CNN / ノイズCNN / LSI / 深層学習 / 組込みシステム / 画像圧縮 / Deep Learning / 計算機システム / 高性能計算 / Noise Convolution
Outline of Research at the Start

学習済みCNNのパラメータの統計的解析に元づく雑音畳込みニューラルネットワーク(雑音CNN)を提案する。雑音CNNは畳込み演算の大部分を雑音の畳込みで代用してパラメータを最大で約90%削減できる。本研究では、雑音CNNの雑音畳み込み回路を開発し、組込み機器向けに専用チップを設計する。また、雑音CNNの学習時間を短縮するため、FPGAベースの高速学習クラスタを開発する。FPGAによるプロトタイプ実装でさらなる性能向上を明らかにする。

Outline of Final Research Achievements

We derived that the noise CNN is equivalent to the existing CNN. We designed a dedicated circuit for noise CNN and implemented an FPGA prototype. We investigated a noise generation circuit suitable for a configuration that combines a noise generation circuit and 1×1 size convolution, and implemented the circuit. We demonstrated the superiority of the proposed method compared to GPU. We further improved the performance of the noisy CNN circuit by applying existing parameter reduction methods such as bit reduction and pruning. Since noise convolution is equivalent to existing convolution, we showed that it can be combined with existing methods. We also constructed an FPGA cluster environment to speed up the learning of noisy CNNs, and investigated the learning method for noisy CNNs.

Academic Significance and Societal Importance of the Research Achievements

電力やデバイスの制約で実現できなかった高度な認識技術が組込み機器に実現できた。また、設計のボトルネックであった学習時間が短縮された。研究期間後は、専用チップ化による更なる性能向上とコスト削減に取り組む予定である。

Report

(6 results)
  • 2023 Annual Research Report   Final Research Report ( PDF )
  • 2022 Annual Research Report
  • 2021 Annual Research Report
  • 2020 Annual Research Report
  • 2019 Annual Research Report
  • Research Products

    (32 results)

All 2023 2022 2021 2020 2019 Other

All Int'l Joint Research (4 results) Journal Article (12 results) (of which Int'l Joint Research: 2 results,  Peer Reviewed: 12 results) Presentation (16 results) (of which Int'l Joint Research: 16 results,  Invited: 1 results)

  • [Int'l Joint Research] Imperial College London(英国)

    • Related Report
      2023 Annual Research Report
  • [Int'l Joint Research] Imperial College London(英国)

    • Related Report
      2022 Annual Research Report
  • [Int'l Joint Research] Imperial College London(英国)

    • Related Report
      2021 Annual Research Report
  • [Int'l Joint Research] Imperial College London(英国)

    • Related Report
      2020 Annual Research Report
  • [Journal Article] Remarn: A Reconfigurable Multi-threaded Multi-core Accelerator for Recurrent Neural Networks2023

    • Author(s)
      Zhiqiang Que, Hiroki Nakahara, Hongxiang Fan, He Li, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Eriko Nurvitadhi, Wayne Luk:
    • Journal Title

      ACM Trans. Reconfigurable Technol.

      Volume: 16 Pages: 1-26

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] Multilayer Perceptron Training Accelerator Using Systolic Array2022

    • Author(s)
      Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
    • Journal Title

      EICE Trans. Inf. Syst.

      Volume: 105-D(12) Pages: 2048-2056

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Recurrent Neural Networks With Column-Wise Matrix-Vector Multiplication on FPGAs2022

    • Author(s)
      Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Andrew Boutros, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Kuen Hung Tsoi, Xinyu Niu, Wayne Luk
    • Journal Title

      IEEE Trans. Very Large Scale Integr. Syst.

      Volume: 30(2) Pages: 227-237

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed / Int'l Joint Research
  • [Journal Article] Optimizations of Ternary Generative Adversarial Networks2022

    • Author(s)
      Kennichi Nakamura, Hiroki Nakahara
    • Journal Title

      IEEE Int. Symp. on Multi-valued Logic (ISMVL)

      Pages: 158-163

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Fast Interface with Ensemble Ternary Neural Network2022

    • Author(s)
      Ryota Kayanoma, Hiroki Nakahara
    • Journal Title

      IEEE Int. Symp. on Multi-valued Logic (ISMVL)

      Pages: 182-187

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Energy-Efficient ECG Signals Outlier Detection Hardware Using a Sparse Robust Deep Autoencoder2021

    • Author(s)
      Naoto Soga, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Trans. Inf. Syst

      Volume: 104-D(8) Pages: 1121-1129

    • NAID

      130008070358

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Weight Sparseness for a Feature-Map-Split-CNN Toward Low-Cost Embedded FPGAs2021

    • Author(s)
      Akira Jinguji, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Trans. Inf. Syst.

      Volume: 104-D(12) Pages: 2040-2047

    • NAID

      130008123390

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Low-Latency Inference of Randomly Wired Convolutional Neural Networks on an FPGA2021

    • Author(s)
      Ryosuke Kuramochi, Hiroki Nakahara
    • Journal Title

      IEICE Trans. Inf. Syst.

      Volume: 104-D(12) Pages: 2068-2077

    • NAID

      130008123389

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] FPGA-Based Inter-layer Pipelined Accelerators for Filter-Wise Weight-Balanced Sparse Fully Convolutional Networks with Overlapped Tiling2021

    • Author(s)
      Masayuki Shimoda, Youki Sada, Hiroki Nakahara
    • Journal Title

      J. Signal Process. Syst.

      Volume: 93(5) Pages: 499-512

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed
  • [Journal Article] SENTEI: Filter-Wise Pruning with Distillation towards Efficient Sparse Convolutional Neural Network Accelerators2020

    • Author(s)
      Masayuki Shimoda, Youki Sada, Ryosuke Kuramochi, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E103.D Issue: 12 Pages: 2463-2470

    • DOI

      10.1587/transinf.2020PAP0013

    • NAID

      130007948567

    • ISSN
      0916-8532, 1745-1361
    • Year and Date
      2020-12-01
    • Related Report
      2020 Annual Research Report
    • Peer Reviewed
  • [Journal Article] GUINNESS: A GUI Based Binarized Deep Neural Network Framework for Software Programmers2019

    • Author(s)
      Hiroki Nakahara, Haruyoshi Yonekawa, Tomoya Fujii, Masayuki Shimoda, Shimpei Sato
    • Journal Title

      IEICE Trans. Inf. Syst.

      Volume: 102-D(5) Pages: 1003-1011

    • NAID

      130007641155

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Power Efficient Object Detector with an Event-Driven Camera for Moving Object Surveillance on an FPGA2019

    • Author(s)
      Masayuki Shimoda, Shimpei Sato, Hiroki Nakahara
    • Journal Title

      IEICE Trans. Inf. Syst.

      Volume: 102-D(5) Pages: 1020-1028

    • NAID

      130007641234

    • Related Report
      2019 Annual Research Report
    • Peer Reviewed
  • [Presentation] A Light-Weight Vision Transformer Toward Near Memory Computation on an FPGA2023

    • Author(s)
      Takeshi Senoo, Ryota Kayanoma, Akira Jinguji, Hiroki Nakahara
    • Organizer
      ARC
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Consideration on Ternary Adversarial Generative Networks2023

    • Author(s)
      Kennichi Nakamura, Hiroki Nakahara
    • Organizer
      ISMVL
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Multilayer Perceptron Training Accelerator using Systolic Array2021

    • Author(s)
      Takeshi Senoo, Akira Jinguji, Ryosuke Kuramochi, Hiroki Nakahara
    • Organizer
      IEEE APCCAS
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Edge Inference Engine for Deep & Random Sparse Neural Networks with 4-bit Cartesian-Product MAC Array and Pipelined Activation Aligner2021

    • Author(s)
      Kota Ando, Jaehoon Yu, Kazutoshi Hirose, Hiroki Nakahara, Kazushi Kawamura, Thiem Van Chu, Masato Motomura
    • Organizer
      IEEE HCS
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A High-Throughput Detection Circuit based on 2q+1-Valued Deep Neural Networks2021

    • Author(s)
      Naoto Soga, Ryosuke Kuramochi, Hiroki Nakahara
    • Organizer
      IEEE ISMVL
    • Related Report
      2021 Annual Research Report
    • Int'l Joint Research
  • [Presentation] High-Throughput Convolutional Neural Network on an FPGA by Customized JPEG Compression2020

    • Author(s)
      Hiroki Nakahara, Zhiqiang Que, Wayne Luk
    • Organizer
      FCCM2020
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Optimizing Reconfigurable Recurrent Neural Networks2020

    • Author(s)
      Zhiqiang Que, Hiroki Nakahara, Eriko Nurvitadhi, Hongxiang Fan, Chenglong Zeng, Jiuxi Meng, Xinyu Niu, Wayne Luk
    • Organizer
      FCCM2020
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] An FPGA-Based Low-Latency Accelerator for Randomly Wired Neural Networks2020

    • Author(s)
      Ryosuke Kuramochi, Hiroki Nakahara
    • Organizer
      FPL2020
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] 2n+1-valued SSS-Net: Uniform Shift, Channel Sparseness, and Channel Shuffle2020

    • Author(s)
      Hiroki Nakahara
    • Organizer
      ISMVL2020
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Fast Monocular Depth Estimation on an FPGA2020

    • Author(s)
      Youki Sada, Naoto Soga, Masayuki Shimoda, Akira Jinguji, Shimpei Sato, Hiroki Nakahara
    • Organizer
      IPDPS Workshops 2020
    • Related Report
      2020 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Filter-Wise Pruning Approach to FPGA Implementation of Fully Convolutional Network for Semantic Segmentation2019

    • Author(s)
      Masayuki Shimoda, Youki Sada, Hiroki Nakahara
    • Organizer
      ARC2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGA-Based Training Accelerator Utilizing Sparseness of Convolutional Neural Network.2019

    • Author(s)
      Hiroki Nakahara, Youki Sada, Masayuki Shimoda, Kouki Sayama, Akira Jinguji, Shimpei Sato
    • Organizer
      FPL2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] A Dataflow Pipelining Architecture for Tile Segmentation with a Sparse MobileNet on an FPGA2019

    • Author(s)
      Youki Sada, Masayuki Shimoda, Akira Jinguji, Hiroki Nakahara
    • Organizer
      FPT 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Noise Convolutional Neural Networks and FPGA Implementation2019

    • Author(s)
      Atsuki Munakata, Hiroki Nakahara, Shimpei Sato
    • Organizer
      ISMVL 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks2019

    • Author(s)
      Ryosuke Kuramochi, Youki Sada, Masayuki Shimoda, Shimpei Sato
    • Organizer
      MCSoC 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Deep Learning Accelerator for an Intelligent Camera2019

    • Author(s)
      Hiroki Nakahara
    • Organizer
      HEART 2019
    • Related Report
      2019 Annual Research Report
    • Int'l Joint Research / Invited

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Published: 2019-04-18   Modified: 2025-01-30  

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