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Elucidation of malfunction mechanisms occurring during switching periods of SiC devices

Research Project

Project/Area Number 19K04351
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 21010:Power engineering-related
Research InstitutionOkayama University

Principal Investigator

Hiraki Eiji  岡山大学, 環境生命自然科学学域, 教授 (20284268)

Co-Investigator(Kenkyū-buntansha) 梅谷 和弘  岡山大学, 自然科学学域, 准教授 (60749323)
Project Period (FY) 2019-04-01 – 2023-03-31
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2022: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2021: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2020: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2019: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Keywordsパワーエレクトロニクス / ワイドギャップ半導体デバイス / 誤動作 / 次世代パワーデバイス / 誤転弧発生メカニズム / 並列駆動 / インバータ / 誤転弧発生メカニズム / 抑制理論 / SiCパワーデバイス / 誤転弧 / 発生メカニズム / 高速スイッチングデバイス / 発生メカニズムの解明
Outline of Research at the Start

SiCベースの次世代半導体パワーデバイスは自ら の高速スイッチング動作が引き起こすスイッチングノイズにより誤動作が発生しやすいと いう欠点を有しており,SiCパワーデバイスの普及に向けた大きな足枷となっている。
本研究は,誤動作のメカニ ズムを分析し,その対策方法を解明する。さらに,実際の電力変換器に本研究で確立した対策 方法を搭載可能にするための回路実装技術を確立する。

Outline of Final Research Achievements

Next-generation wide-bandgap power semiconductor devices, such as SiC and GaN, are expected to make significant contributions to the energy problem. However, their penetration into society has not progressed as much as initially anticipated. One major reason for this is the occurrence of malfunctions due to self-generated noise when attempting to maximize the "high-speed switching performance" inherent in these next-generation power semiconductor devices. It has been reported that the conventional approach of minimizing wire length, which is known to mitigate this issue, is often ineffective.
In this study, we have identified countermeasures against malfunctions that still occur even after making efforts to minimize wire length. Furthermore, we have established circuit implementation techniques to apply these countermeasures to practical devices.

Academic Significance and Societal Importance of the Research Achievements

パワー半導体デバイスの誤動作を電気回路的にモデリングし,誤動作の抑制条件を具体的な回路パラメータの設計条件として示すことで,従来の経験的な視点による対策では対処できなかった問題に対する明確な指針を示すことができた。この成果は,これからのパワーエレクトロニクス分野,ひいては地球規模でのエネルギー問題に大きく貢献することになるであろう。

Report

(5 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • Research Products

    (6 results)

All 2022 2021 2020

All Presentation (6 results) (of which Int'l Joint Research: 3 results)

  • [Presentation] 電気自動車用インバータの高電力密度化に向けたGaN-HEMT実装方法の提案2022

    • Author(s)
      竹原 佑,石原 將貴,梅谷 和弘,平木 英治
    • Organizer
      パワーエレクトロニクス学会第246回定例研究会
    • Related Report
      2022 Annual Research Report
  • [Presentation] 小型EV向け高電力密度インバータ実現に向けて低寄生インダクタンス・高放熱性能を両立するためのアルミ基板を用いたGaN-HEMT実装方法の提案2022

    • Author(s)
      竹原 佑,石原將貴,梅谷和弘,平木英治
    • Organizer
      電気学会D部門 半導体電力変換/モータドライブ合同研究会
    • Related Report
      2022 Annual Research Report
  • [Presentation] Feasibility of Parasitic Drain Inductance Design for Minimizing Switching Loss in Bridge Circuits Using GaN-FETs2021

    • Author(s)
      Koki Abe, Masataka Ishihara, Yusuke Hatakenaka, Kazuhiro Umetani, Eiji Hiraki,
    • Organizer
      IEEE 2021 30th International Symposium on Industrial Electronics (ISIE2021)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] Parasitic Inductance Design for Preventing Oscillatory False Triggering of Parallel-Connected GaN-FETs2021

    • Author(s)
      Yusuke Hatakenaka, Kazuhiro Umetani, Masataka Ishihara, Eiji Hiraki, Hiroshi Tadano
    • Organizer
      IEEE 2021 47th Annual Conference of the IEEE Industrial Electronics Society (IECON2021)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] Optimization of Common Source Inductance and Gate-Drain Capacitance for Reducing Gate Voltage Fluctuation after Turn-off Transition2020

    • Author(s)
      Yusuke Hatakenaka, Kazuhiro Umetani, Masataka Ishihara, Eiji Hiraki
    • Organizer
      EEE Energy Conversion Conf. Expo. (ECCE2020), Oct. 2020
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research
  • [Presentation] アルミコア基板を用いた三相PWMインバータの熱設計2020

    • Author(s)
      秋間雅宏,小西晃央,梅谷和弘,平木英治
    • Organizer
      パワーエレクトロニクス学会
    • Related Report
      2020 Research-status Report

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Published: 2019-04-18   Modified: 2024-01-30  

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