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Automatic synthesis of memory access optimization programs synergistically coordinated with deep learning and empirical methods

Research Project

Project/Area Number 19K11874
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 60040:Computer system-related
Research InstitutionToyohashi University of Technology

Principal Investigator

Sato Yukinori  豊橋技術科学大学, 工学(系)研究科(研究院), 准教授 (30452113)

Project Period (FY) 2019-04-01 – 2023-03-31
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2022: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2021: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2020: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2019: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Keywordsメモリアクセス最適化 / 性能モデル / ハード・ソフト協調設計 / 深層学習と経験的手法 / プログラム自動合成
Outline of Research at the Start

近年の深層学習技術の進展は目覚ましい反面、これらの成果を社会に幅広く展開するためには性能・電力・コストの面で最適化された深層学習処理向けのシステムアーキテクチャを探求していくことが急務である。このような状況の下、ハード・ソフトにまたがる広大なアーキテクチャ設計空間に対して深層学習を活用し、既存の高位最適化コンパイラに実装されている経験的手法と協調しながら動作する最適化器の自動合成を試みる。実環境での観測に基づく大量の教師学習データに駆動される形で対応可能となる最適化器の自動合成法を研究開発することにより、深層学習向けシステムアーキテクチャ技術の本質を追求していくことを目指す。

Outline of Final Research Achievements

Toward automatic synthesis of memory access optimization programs, we tackled with synergistically coordinated with deep learning and empirical methods. For the deep learning part, we investigated optimization methods that exploit graph neural networks to smoothly cooperate with code optimization techniques for executable code. From the results of prototype implementation, we obtained some insights for further research. For the empirical method part, we investigated on the Polyhedral model and a cache simulator as a performance model against systems with complex memory hierarchy. From the results of evaluation, we demonstrated that our techniques developed in this work can be applied to a productive performance profiling tool and a simulator that assesses the memory reliability of systems.

Academic Significance and Societal Importance of the Research Achievements

近年の深層学習技術の進展は目覚ましい反面、これらの成果を社会に幅広く展開するためには性能・電力・コストの面で最適化された深層学習処理向けのシステムアーキテクチャを探求していくことが急務である。このような状況の下、ハード・ソフトにまたがる広大なアーキテクチャ設計空間に対して最適化を行う機構の自動合成を目指すのが本研究の目的であった。プログラマによる手作業では手に負えなくなる規模の複雑かつ明示的で緻密な場合分けが必要となる最適化であっても、経験的手法を性能モデルと連携する形で拡張させていくことにより自動化できる可能性が示された。

Report

(5 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • Research Products

    (7 results)

All 2022 2021

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (4 results) (of which Int'l Joint Research: 3 results)

  • [Journal Article] ベリファイ機構を搭載したVC-MRAMに対するシステムレベルシミュレーション2022

    • Author(s)
      斉藤 大貴, 広渕 崇宏, 荒井 礼子, 佐藤 幸紀
    • Journal Title

      The 6th cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2022)

      Volume: - Pages: 1-10

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM2021

    • Author(s)
      Saito Daiki、Hirofuchi Takahiro、Arai Hiroko、Sato Yukinori
    • Journal Title

      Proceedings of the 2021 Ninth International Symposium on Computing and Networking Workshops (CANDARW)

      Volume: 1 Pages: 120-126

    • DOI

      10.1109/candarw53999.2021.00027

    • Related Report
      2021 Research-status Report
    • Peer Reviewed
  • [Journal Article] Thread-Aware Cache Simulator for HPC Application Tuning2021

    • Author(s)
      Chugo Kazuki、Sato Yukinori
    • Journal Title

      In Proceedings of 12th International Workshop on Advances in Networking and Computing (WANC 2021)

      Volume: - Pages: 424-428

    • DOI

      10.1109/candarw53999.2021.00078

    • Related Report
      2021 Research-status Report
    • Peer Reviewed
  • [Presentation] ベリファイ機構を搭載したVC-MRAMに対するシステムレベルシミュレーション2022

    • Author(s)
      斉藤 大貴, 広渕 崇宏, 荒井 礼子, 佐藤 幸紀
    • Organizer
      The 6th cross-disciplinary Workshop on Computing Systems, Infrastructures, and Programming (xSIG 2022)
    • Related Report
      2022 Annual Research Report
  • [Presentation] A simulation of a memory subsystem using a highly energy-efficient but erroneous MRAM2021

    • Author(s)
      Daiki Saito, Takahiro Hirofuchi, Hiroko Arai, Yukinori Sato
    • Organizer
      9th International Workshop on Computer Systems and Architectures (CSA 2021)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] Thread-Aware Cache Simulator for HPC Application Tuning2021

    • Author(s)
      Kazuki Chugo, Yukinori Sato
    • Organizer
      12th International Workshop on Advances in Networking and Computing (WANC 2021)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research
  • [Presentation] An Online Trace-Driven Cache Simulator for ARM-Based Supercomputers2021

    • Author(s)
      Kazuki Chugo, Yukinori Sato
    • Organizer
      Poster presentation, IEEE Symposium on Low-Power and High-Speed Chips and Systems (COOL Chips 24)
    • Related Report
      2020 Research-status Report
    • Int'l Joint Research

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Published: 2019-04-18   Modified: 2024-01-30  

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