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High Speed FPGA Simulator for Large Scale Quantum Annealing Simulations

Research Project

Project/Area Number 19K11998
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 60100:Computational science-related
Research InstitutionTohoku University

Principal Investigator

Waidyasooriya Hasitha  東北大学, 情報科学研究科, 准教授 (60723533)

Project Period (FY) 2019-04-01 – 2023-03-31
Project Status Completed (Fiscal Year 2022)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2022: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2021: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2020: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2019: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Keywords量子アニーリングシミュレーション / FPGA / カスタムアクセラレータ / 組合せ最適化問題 / 量子アニーリング / FPGAアクセラレータ / 組み合わせ最適化問題 / 並列計算
Outline of Research at the Start

交通量,津波などの各類のシミュレーション,グラフ解析,人工知能などの分野では最適解を高速に見つけることは重要である.近年,量子アニーリングシミュレーションが最適解を見つける手法として注目されている.その実装方法として,量子コンピュータやCPU/GPUが用いられている.量子コンピュータでは使える問題規模が小さいことは課題である.本研究ではFPGAアクセラレータを提案しCPUの数千倍から数万倍の性能向上を達成することを目的とする.FPGAとは応用により回路構成を変更可能なプログラマブル集積回路であり,大量の演算器を柔軟に接続し最適な回路構成を構築することにより高並列な処理を実現できる.

Outline of Final Research Achievements

(1) Large scale quantum annealing simulation: The connections among spins (coefficients) increases exponentially with the number of spins. This increases the required memory capacity and prevents large-scale simulation. This research proposes a method to generate the coefficients efficiently, without storing the pre-generated coefficients in the memory. As a result, large memory requirement has been eliminated, and we were able to run simulations with over 200,000 spins using a single FPGA.
(2) Acceleration: Quantum Monte-Carlo method used for the simulations is very difficult to parallelize. We proposed a method to execute the computations among multiple Trotter slices in parallel while maintaining the data dependancy. As a result, we achieved over 290 times speed-up compared to CPU serial implementation.
(3) High accuracy: Since we protect the data dependency in parallel computation, the accuracy is very high. Compared to D-Wave using MQLib benchmark suit, the accuracy is over 99%.

Academic Significance and Societal Importance of the Research Achievements

量子アニーリングは最適化において重要な手法であり,交通量シミュレーション,工場の作業の最適化,避難経路最適化などの様々な実用的な問題を効率的に解くことができると知られている.しかしながら,実問題は大規模であり,D-Waveなどの量子アニーラーを用いる事は難しい.本研究プロジェクトでは20万スピン以上に全結合シミュレーションができており,複数FPGAを使う場合はさらに大規模化ができる可能性を示した.さらにCPUの290倍以上の高速性を99%以上の高い計算制度で達成できた.また,GPUやマルチコアCPUを用いた高速化も提案されており,社会的な最適化問題に応用できる可能性は十分示している.

Report

(5 results)
  • 2022 Annual Research Report   Final Research Report ( PDF )
  • 2021 Research-status Report
  • 2020 Research-status Report
  • 2019 Research-status Report
  • Research Products

    (19 results)

All 2022 2021 2020 2019

All Journal Article (7 results) (of which Int'l Joint Research: 5 results,  Peer Reviewed: 7 results,  Open Access: 6 results) Presentation (12 results) (of which Int'l Joint Research: 11 results,  Invited: 2 results)

  • [Journal Article] A Scalable Emulator for Quantum Fourier Transform Using Multiple-FPGAs With High-Bandwidth-Memory2022

    • Author(s)
      Waidyasooriya Hasitha Muthumala、Oshiyama Hiroki、Kurebayashi Yuya、Hariyama Masanori、Ohzeki Masayuki
    • Journal Title

      IEEE Access

      Volume: 10 Pages: 65103-65117

    • DOI

      10.1109/access.2022.3183993

    • Related Report
      2022 Annual Research Report
    • Peer Reviewed / Open Access / Int'l Joint Research
  • [Journal Article] Temporal and spatial parallel processing of simulated quantum annealing on a multicore CPU2022

    • Author(s)
      Waidyasooriya Hasitha Muthumala、Hariyama Masanori
    • Journal Title

      The Journal of Supercomputing

      Volume: 78 Issue: 6 Pages: 8733-8750

    • DOI

      10.1007/s11227-021-04242-0

    • Related Report
      2021 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] Design space exploration for an FPGA-based quantum annealing simulator with interaction-coefficient-generators2021

    • Author(s)
      Liu Chia-Yin、Waidyasooriya Hasitha Muthumala、Hariyama Masanori
    • Journal Title

      The Journal of Supercomputing

      Volume: 78 Issue: 1 Pages: 1-17

    • DOI

      10.1007/s11227-021-03859-5

    • Related Report
      2021 Research-status Report
    • Peer Reviewed / Open Access
  • [Journal Article] A GPU-Based Quantum Annealing Simulator for Fully-Connected Ising Models Utilizing Spatial and Temporal Parallelism2020

    • Author(s)
      Waidyasooriya Hasitha Muthumala、Hariyama Masanori
    • Journal Title

      IEEE Access

      Volume: 8 Pages: 67929-67939

    • DOI

      10.1109/access.2020.2985699

    • Related Report
      2020 Research-status Report
    • Peer Reviewed / Open Access / Int'l Joint Research
  • [Journal Article] FPGA-accelerated Searchable Encrypted Database Management Systems for Cloud Services2020

    • Author(s)
      Okada Mitsuhiro、Suzuki Takayuki、Nishio Naoya、Waidyasooriya Hasitha、Hariyama Masanori
    • Journal Title

      IEEE Transactions on Cloud Computing

      Volume: - Issue: 2 Pages: 1373-1385

    • DOI

      10.1109/tcc.2020.2969655

    • Related Report
      2019 Research-status Report
    • Peer Reviewed / Open Access / Int'l Joint Research
  • [Journal Article] Multi-FPGA Accelerator Architecture for Stencil Computation Exploiting Spacial and Temporal Scalability2019

    • Author(s)
      Waidyasooriya Hasitha Muthumala、Hariyama Masanori
    • Journal Title

      IEEE Access

      Volume: 7 Pages: 53188-53201

    • DOI

      10.1109/access.2019.2910824

    • Related Report
      2019 Research-status Report
    • Peer Reviewed / Open Access / Int'l Joint Research
  • [Journal Article] Highly-Parallel FPGA Accelerator for Simulated Quantum Annealing2019

    • Author(s)
      Waidyasooriya Hasitha、Hariyama Masanori
    • Journal Title

      IEEE Transactions on Emerging Topics in Computing

      Volume: - Issue: 4 Pages: 2019-2029

    • DOI

      10.1109/tetc.2019.2957177

    • Related Report
      2019 Research-status Report
    • Peer Reviewed / Int'l Joint Research
  • [Presentation] Implementation of an FPGA-Oriented Complex Number Computation Library Using Intel OneAPI DPC++2022

    • Author(s)
      Kosiro Obata, Hasitha Muthumala Waidyasooriya and Masanori Hariyama
    • Organizer
      IEEE International Midwest Symposium on Circuits and Systems
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] OpenCL-Based Design of an FPGA Accelerator for H.266/VVC Transform and Quantization2022

    • Author(s)
      Hasitha Muthumala Waidyasooirya, Masanori Hariyama, Hiroe Iwasaki, Daisuke Kobayashi, Yuya Omori, Ken Nakamura, Koyo Nitta, and Kimikazu Sano
    • Organizer
      IEEE International Midwest Symposium on Circuits and Systems
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGA Acceleration of Quantum Annealing Simulations2022

    • Author(s)
      Hasitha Muthumala Waidyasooirya
    • Organizer
      Japan-Taiwan Advanced Quantum Technology Research and Development Workshop
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research / Invited
  • [Presentation] Direct Mapping of Neural Circuits on FPGA2022

    • Author(s)
      Mizuki Harasawa, Hasitha Muthumala Waidyasooirya and Masanori Hariyama
    • Organizer
      23rd International Conference on Parallel and Distributed Computing, Applications and Technologies
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Scalable Architecture Targeting HBM-Based FPGAs for Complex Matrix Multiplication2022

    • Author(s)
      Hasitha Muthumala Waidyasooirya, Takuro Fukuda and Masanori Hariyama
    • Organizer
      23rd International Conference on Parallel and Distributed Computing, Applications and Technologies
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Word2Vec FPGA Accelerator Based on Spatial and Temporal Parallelism2022

    • Author(s)
      Hasitha Muthumala Waidyasooirya, Shutaro Ishihara and Masanori Hariyama
    • Organizer
      23rd International Conference on Parallel and Distributed Computing, Applications and Technologies
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGA-based Prototype of a Quantum Annealing Simulator for Sparse Ising Model2022

    • Author(s)
      Hasitha Muthumala Waidyasooirya, Yuta Ohma and Masanori Hariyama
    • Organizer
      15th IEEE International Symposium on Embedded Multicore/Many-coreSystems-on-Chip
    • Related Report
      2022 Annual Research Report
    • Int'l Joint Research
  • [Presentation] FPGA-based Custom Supercomputing for Intelligent Systems2021

    • Author(s)
      Hasitha Muthumala Waidyasooirya
    • Organizer
      2021 Bilateral Workshop between Tohoku University and National Tsing Hua University
    • Related Report
      2021 Research-status Report
    • Invited
  • [Presentation] FPGA-Based Acceleration of Word2vec using OpenCL2019

    • Author(s)
      Taisuke Ono, Tomoki Shoji, Hasitha Muthumala Waidyasooriya, Masanori Hariyama. Yuichiro Aoki, Yuki Kondoh, and Yaoko Nakagawa
    • Organizer
      International Symposium on Circuits and Systems (ISCAS 2019)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Hasitha Muthumala Waidysooriya, Yasuaki Iimura, and Masanori Hariyama2019

    • Author(s)
      Benchmarks for FPGA-Targeted High-Level-Synthesis
    • Organizer
      7th International Symposium on Computing and Networking (CANDAR)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] Data-Transfer-Bottleneck-Less Architecture for FPGA-Based Quantum Annealing Simulation2019

    • Author(s)
      Chia-Yin Liu, Hasitha Muthumala Waidysooriya, and Masanori Hariyama
    • Organizer
      7th International Symposium on Computing and Networking (CANDAR)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research
  • [Presentation] A Memory-Bandwidth-Efficient Word2vec Accelerator Using OpenCL for FPGA2019

    • Author(s)
      Tomoki Shoji, Taisuke Ono, Hasitha Muthumala Waidyasooriya, Masanori Hariyama. Yuichiro Aoki, Yuki Kondoh, and Yaoko Nakagawa
    • Organizer
      7th International Symposium on Computing and Networking (CANDAR)
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research

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Published: 2019-04-18   Modified: 2024-01-30  

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