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Fabrication of Direct Bandgap Group-IV Semiconductors by Utilizing Sn Alloying Technique Based on Rapid Melting Growth and Its Electrical Characterization

Research Project

Project/Area Number 19K15035
Research Category

Grant-in-Aid for Early-Career Scientists

Allocation TypeMulti-year Fund
Review Section Basic Section 21050:Electric and electronic materials-related
Research InstitutionNational Institute of Advanced Industrial Science and Technology

Principal Investigator

Oka Hiroshi  国立研究開発法人産業技術総合研究所, エレクトロニクス・製造領域, 研究員 (10828007)

Project Period (FY) 2019-04-01 – 2022-03-31
Project Status Completed (Fiscal Year 2021)
Budget Amount *help
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2021: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2020: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2019: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Keywordsゲルマニウムスズ / 固相成長 / フラッシュランプアニール / MOSFET / CMOS / 固相結晶化 / トランジスタ / 溶融結晶化 / ナノワイヤトランジスタ
Outline of Research at the Start

近年、ゲルマニウム(Ge)に同じくIV族の半金属であるスズ(Sn)を一定以上(約10%)添加することでバンド構造が間接遷移型から直接遷移型に変調し、キャリア移動度が劇的に向上することが理論予測されている。
しかしGe中のSnの熱平衡固溶限は1%以下と低く、またSnの低い融点が混晶材料設計の大きな障害となっている。本研究ではこれらの課題に対し、急速溶融結晶化をベースとしたSn濃縮添加技術を提案し、シリコン(Si)プラットフォーム上での直接遷移型GeSnナノワイヤトランジスタ創製とSn組成・歪み量に対する電子物性の系統的評価を目的とする。

Outline of Final Research Achievements

We demonstrated the high-performance GeSn n-MOSFET based on high-Sn content GeSn layer fabricated by the milli-second flash lamp annealing (FLA). FLA processing enables the solid-phase growth of the amorphous GeSn layer without out-diffusion or segregation of Sn atoms, providing the high-Sn content crystalline GeSn with Sn content over 10%, which far exceeds the solid solubility. Furthermore, a high-quality n+/p junction was successfully formed by using FLA activation annealing. By combining the FLA solid-phase growth and FLA activation annealing, high-Sn content GeSn n-MOSFET with enhanced on-current and improved switching characteristics was achieved, which clearly indicates the advantage of FLA processing for the high-mobility GeSn-CMOS.

Academic Significance and Societal Importance of the Research Achievements

GeSn MOSFETのチャネルSn高濃度化を目指す上で、Snの低い固溶限(1%)が大きな技術的課題であった。本研究ではミリ秒の急速加熱が可能なFLAプロセスを用いることで、Snの固溶限界を超えたGeSnチャネルの実現が可能であることを実証した。高移動度CMOSチャネルに向けた薄膜成長手法の新しいアプローチである。

Report

(4 results)
  • 2021 Annual Research Report   Final Research Report ( PDF )
  • 2020 Research-status Report
  • 2019 Research-status Report
  • Research Products

    (4 results)

All 2021 2020 2019

All Journal Article (2 results) (of which Peer Reviewed: 2 results,  Open Access: 2 results) Presentation (2 results) (of which Int'l Joint Research: 1 results)

  • [Journal Article] Flash lamp annealing processing to improve the performance of high-Sn content GeSn n-MOSFETs2021

    • Author(s)
      Oka Hiroshi、Mizubayashi Wataru、Ishikawa Yuki、Uchida Noriyuki、Mori Takahiro、Endo Kazuhiko
    • Journal Title

      Applied Physics Express

      Volume: 14 Issue: 9 Pages: 096501-096501

    • DOI

      10.35848/1882-0786/ac1a47

    • Related Report
      2021 Annual Research Report
    • Peer Reviewed / Open Access
  • [Journal Article] Non-equilibrium solid-phase growth of amorphous GeSn layer on Ge-on-insulator wafer induced by flash lamp annealing2021

    • Author(s)
      Oka Hiroshi、Mizubayashi Wataru、Ishikawa Yuki、Uchida Noriyuki、Mori Takahiro、Endo Kazuhiko
    • Journal Title

      Applied Physics Express

      Volume: 14 Issue: 2 Pages: 025505-025505

    • DOI

      10.35848/1882-0786/abdac4

    • Related Report
      2020 Research-status Report
    • Peer Reviewed / Open Access
  • [Presentation] Solid-phase Grown GeSn n-MOSFETs on GOI Wafer Fabricated by Flash Lamp Annealing2020

    • Author(s)
      H. Oka, W. Mizubayashi, T. Mori, Y. Ishikawa, T. Hosoi, T. Shimura, H. Watanabe, and K. Endo
    • Organizer
      第25回電子デバイス界面テクノロジー研究会
    • Related Report
      2019 Research-status Report
  • [Presentation] Tensile-strained GeSn-on-SOI MSM Photodetector Fabricated by Solid-phase Epitaxy2019

    • Author(s)
      H. Oka, W. Mizubayashi, T. Hosoi, T. Shimura, H. Watanabe, T. Maeda, N. Uchida, K. Endo
    • Organizer
      JST-MOST Joint Workshop on "Nanoelectronics and System Integration for AI"
    • Related Report
      2019 Research-status Report
    • Int'l Joint Research

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Published: 2019-04-18   Modified: 2023-01-30  

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