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ソースヘテロ構造を用いたバリスティック素子の基盤研究

Research Project

Project/Area Number 20035014
Research Category

Grant-in-Aid for Scientific Research on Priority Areas

Allocation TypeSingle-year Grants
Review Section Science and Engineering
Research InstitutionKanagawa University

Principal Investigator

水野 智久  Kanagawa University, 理学部, 教授 (60386810)

Co-Investigator(Kenkyū-buntansha) 鮫島 俊之  東京農工大学, 共生科学技術研究院, 教授 (30271597)
Project Period (FY) 2008 – 2010
Project Status Completed (Fiscal Year 2009)
Budget Amount *help
¥4,600,000 (Direct Cost: ¥4,600,000)
Fiscal Year 2009: ¥2,300,000 (Direct Cost: ¥2,300,000)
Fiscal Year 2008: ¥2,300,000 (Direct Cost: ¥2,300,000)
Keywords電子デバイス / 半導体物性 / マイクロ・ナノデバイス
Research Abstract

1.Cイオン注入及びレーザーアニール装置によるSi_<1-x>C_x層の形成実験,及びその物性評価
薄膜SOI基板にCイオン注入後,レーザ加熱を行うことによって,Si-C結合によるラマンピークを検出した.その結果,本作成方法によって,SiとCとの結合を実証できた.
2.デバイスシミュレータを用いた素子構造設計その2
ソースヘテロ端でのキャリアのトンネル効果を考慮したシミュレータを用い,サブ10nm-SHOT素子における駆動能力のヘテロバンドオフセット最依存性をn及びpチャネルにおいても明確にした.
3.新構造ヘテロの検討
歪SOI基板を用いて,緩和/歪層による新たなソースヘテロ構造を実現した.これは,Oイオン注入法を用いて,その反跳エネルギーによって,歪みSi/埋め込み酸化膜界面での歪みSiの滑りにより局所的に歪みを緩和させることにより実現できた.

Report

(2 results)
  • 2009 Annual Research Report
  • 2008 Annual Research Report

Research Products

(9 results)

All 2010 2009 2008

All Journal Article Presentation Patent(Industrial Property Rights)

  • [Journal Article] New Source Heterojunction Structures with Relaxed/Strainal Semiconductors for Quasi-Ballistic Complementary Metal-Oxide-Semiconductor Transistors : Relaxation Technique of Strained Substrates and Design of Sub-10nm Devices2010

    • Author(s)
      Tomohisa Mizuno, Naoki Mizoguchi, Kotaio Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, Tsutomu Tezuka
    • Journal Title

      Jpn.J.Appl.Phys. 49

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates2009

    • Author(s)
      T.Mizuno, N.Mizoguchi, K..Tanimoto, T.Yamauchi, T.Tezuka, T.Sameshima
    • Journal Title

      Ext.Ahstr.SSDM

      Pages: 769-770

    • Related Report
      2009 Annual Research Report
    • Peer Reviewed
  • [Presentation] 巣一半導体を用いた新ソースヘテロ構造の検討(II):CMOS川緩和/歪半導体構造2010

    • Author(s)
      水野智久, 長谷川光央, 鮫島俊之
    • Organizer
      応用物理学会
    • Place of Presentation
      東海大学
    • Year and Date
      2010-03-17
    • Related Report
      2009 Annual Research Report
  • [Presentation] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates2009

    • Author(s)
      T.Mizuno, N.Mizoguchi, K.Tanimoto, T.Yamauchi, T.Tezuka, T.Sameshima
    • Organizer
      SSDM
    • Place of Presentation
      Sendai
    • Year and Date
      2009-10-08
    • Related Report
      2009 Annual Research Report
  • [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討:(I)緩和Si/歪Siヘテロ構造2009

    • Author(s)
      水野智久, 溝口直樹, 谷本光太郎, 山内知明, 鮫島俊之
    • Organizer
      応用物理学会
    • Place of Presentation
      富山大学
    • Year and Date
      2009-09-10
    • Related Report
      2009 Annual Research Report
  • [Presentation] ソースヘテロ素子構造の最適化実験2008

    • Author(s)
      水野智久, 守山佳彦, 手塚勉, 杉山直治, 高木信一
    • Organizer
      応物学会
    • Place of Presentation
      中部大学
    • Year and Date
      2008-09-14
    • Related Report
      2008 Annual Research Report
  • [Presentation] Experimental Study for Ballistic MOSFETs using Source-Heterojunction Band Offset Structures2008

    • Author(s)
      T. Mizuno, T. Tezuka, N. Sugiyama, and S. Takagi
    • Organizer
      NSC-JST Nano Device Workshop
    • Place of Presentation
      Taipei, Taiwan
    • Year and Date
      2008-07-31
    • Related Report
      2008 Annual Research Report
  • [Presentation] Experimental Study of Single Source-Heterojunction MOS Transistors (SHOTs) Under Ouasi-Ballistic Transport2008

    • Author(s)
      T. Mizuno, Y. Moriyama, T. Tezuka, N. Sugiyama, S. Takagi
    • Organizer
      Symp. VLSI Tech
    • Place of Presentation
      Honolulu, USA
    • Year and Date
      2008-06-17
    • Related Report
      2008 Annual Research Report
  • [Patent(Industrial Property Rights)] 半導体素子構造の形成方法、及び半導体素子2009

    • Inventor(s)
      水野智久
    • Industrial Property Rights Holder
      学校法人神奈川大学
    • Industrial Property Number
      2009-208652
    • Filing Date
      2009-09-09
    • Application Year
      2009
    • Related Report
      2009 Annual Research Report

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Published: 2008-04-01   Modified: 2018-03-28  

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