| Budget Amount *help |
¥11,570,000 (Direct Cost: ¥8,900,000、Indirect Cost: ¥2,670,000)
Fiscal Year 2010: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2009: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2008: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
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| Research Abstract |
We have developed a carry select adder which can be tested by a test set whose cardinality is independent of the operand size, and a parallel prefix adder which can be tested by a test set whose cardinality is proportional to the depth of the circuit. For multiplier design, we have developed a 4-2 adder tree, as well as other adder trees, which can be tested by a test set whose cardinality is independent of the operand size, and also shown that any partial product compressor consisting of carry save adders can be tested by a test set whose cardinality is proportional to the depth of the circuit. We have also developed a prototype tool for synthesizing easily testable parallel prefix adders and 4-2 adder trees.
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