Research on synthesis of easily-testable arithmetic circuits
| Project/Area Number |
20300016
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Nagoya University |
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Principal Investigator |
TAKAGI Naofumi Nagoya University, 大学院・情報学研究科, 教授 (10171422)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAGI Kazuyoshi 名古屋大学, 大学院・情報科学研究科, 准教授 (70273844)
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| Co-Investigator(Renkei-kenkyūsha) |
NAKAMURA Kazuhiro 名古屋大学, 大学院・情報科学研究科, 助教 (90335076)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥11,570,000 (Direct Cost: ¥8,900,000、Indirect Cost: ¥2,670,000)
Fiscal Year 2010: ¥2,080,000 (Direct Cost: ¥1,600,000、Indirect Cost: ¥480,000)
Fiscal Year 2009: ¥5,330,000 (Direct Cost: ¥4,100,000、Indirect Cost: ¥1,230,000)
Fiscal Year 2008: ¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
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| Keywords | VLSIのテスト / 算術演算回路 / 乗算器 / 加算器 / テスト容易化設計 |
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| Research Abstract |
We have developed a carry select adder which can be tested by a test set whose cardinality is independent of the operand size, and a parallel prefix adder which can be tested by a test set whose cardinality is proportional to the depth of the circuit. For multiplier design, we have developed a 4-2 adder tree, as well as other adder trees, which can be tested by a test set whose cardinality is independent of the operand size, and also shown that any partial product compressor consisting of carry save adders can be tested by a test set whose cardinality is proportional to the depth of the circuit. We have also developed a prototype tool for synthesizing easily testable parallel prefix adders and 4-2 adder trees.
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Report
(4 results)
Research Products
(22 results)
