Model abstraction for accelerating TLM verification and test pattern generation
| Project/Area Number |
20300020
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Kyushu University |
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Principal Investigator |
MATSUNAGA Yusuke Kyushu University, システム情報科学研究院, 准教授 (00336059)
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| Co-Investigator(Kenkyū-buntansha) |
BABA Kensuke 九州大学, 付属図書館研究開発室, 准教授 (70380681)
YOSHIMURA Masayoshi 九州大学, システム情報科学研究院, 助教 (90452820)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥18,070,000 (Direct Cost: ¥13,900,000、Indirect Cost: ¥4,170,000)
Fiscal Year 2010: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000)
Fiscal Year 2009: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000)
Fiscal Year 2008: ¥8,320,000 (Direct Cost: ¥6,400,000、Indirect Cost: ¥1,920,000)
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| Keywords | システムLSI / システムレベル検証 / テストパタン生成 |
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| Research Abstract |
This research project is focusing to develop fundamental acceleration techniques for verification methodology on Transaction-Level Model. As outputs of the project, TLM translator, SMT solver, and logic synthesizer for FPGAs aiming to accelerate TLM simulation are developed.
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Report
(4 results)
Research Products
(19 results)
