Model abstraction for accelerating TLM verification and test pattern generation

• Project/Area Number: 20300020
• Research Category: Grant-in-Aid for Scientific Research (B)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Kyushu University
• Principal Investigator: MATSUNAGA Yusuke Kyushu University, システム情報科学研究院, 准教授 (00336059)
• Co-Investigator(Kenkyū-buntansha): BABA Kensuke 九州大学, 付属図書館研究開発室, 准教授 (70380681) ; YOSHIMURA Masayoshi 九州大学, システム情報科学研究院, 助教 (90452820)
• Project Period (FY): 2008 – 2010
• Project Status: Completed (Fiscal Year 2010)
• Budget Amount: ¥18,070,000 (Direct Cost: ¥13,900,000、Indirect Cost: ¥4,170,000); Fiscal Year 2010: ¥4,940,000 (Direct Cost: ¥3,800,000、Indirect Cost: ¥1,140,000); Fiscal Year 2009: ¥4,810,000 (Direct Cost: ¥3,700,000、Indirect Cost: ¥1,110,000); Fiscal Year 2008: ¥8,320,000 (Direct Cost: ¥6,400,000、Indirect Cost: ¥1,920,000)
• Keywords: システムLSI / システムレベル検証 / テストパタン生成

Research Abstract

This research project is focusing to develop fundamental acceleration techniques for verification methodology on Transaction-Level Model. As outputs of the project, TLM translator, SMT solver, and logic synthesizer for FPGAs aiming to accelerate TLM simulation are developed.

Research Products

• [Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-based FPGAs (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Journal Title: IFICE Trans.on Fundamentals Vol. E92-A,No.12
  • NAID: 10026861820
  • Peer Reviewed
• [Journal Article] Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.2 Pages: 200-211
  • NAID: 110009598036
  • Peer Reviewed
• [Journal Article] Framework for Parallel Prefix Adder Synthesis Considering Switching Activities (2009)
  • Author(s): Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Vol.2 Pages: 212-221
  • NAID: 110009598037
  • Peer Reviewed
• [Journal Article] Binding Refinement for Multiplexer Reduction (2009)
  • Author(s): Sho Kodama, Yusuke Matsunaga
  • Journal Title: Transactions on System LSI Design Methodology Vol.2,No.2 Pages: 43-52
  • NAID: 130000120664
  • Peer Reviewed
• [Journal Article] Efficient Cut Enumeration Heuristics for Depth-Optimum Technology Mapping for LUT-Based FPGAs (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Journal Title: IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences Volume: Vol.E92.A, No.12 Pages: 3268-3275
  • NAID: 10026861820
  • Peer Reviewed
• [Journal Article] Area Recovery under Depth Constraint for Technology Mapping for LUT-based FPGAs (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: Vol.2 Pages: 200-211
  • NAID: 110009598036
  • Peer Reviewed
• [Journal Article] Binding Refinement for Multiplexer Reduction (2009)
  • Author(s): Sho Kodama, Yusuke Matsunaga
  • Journal Title: Transcations on System LSI Design Methodology Vol.2 Pages: 43-52
  • NAID: 130000120664
  • Peer Reviewed
• [Journal Article] A Behavioral Synthesis Method with Special Functional Units (2008)
  • Author(s): Tsuyoshi Sadakata, Yusuke Matsunaga
  • Journal Title: IEICE Trans.On Fundamentals Vol.E91-A Pages: 1084-1091
  • NAID: 10026848672
  • Peer Reviewed
• [Presentation] TMR based Error Correction Method Considering Trade-offs between Soft Error Tolerance and Area (2010)
  • Author(s): Shoji Harada, Masayoshi Yoshimura, Yusuke Matsunaga
  • Organizer: International Workshop on Logic and Synthesis
  • Place of Presentation: 米国カリフォルニア州
  • Year and Date: 2010-06-18
• [Presentation] 高位合成における種々の最適化手法について (2010)
  • Author(s): 松永裕介
  • Organizer: 第23回回路とシステム軽井沢ワークショップ
  • Place of Presentation: 長野県,招待講演
  • Year and Date: 2010-04-19
• [Presentation] 高位合成における種々の最適化手法について (2010)
  • Author(s): 松永裕介
  • Organizer: 第23回回路とシステム軽井沢ワークショップ
  • Place of Presentation: 軽井沢プリンスホテル(長野県)
  • Year and Date: 2010-04-19
• [Presentation] A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Organizer: Proc.of International Workshop on Logic and Synthesis 2009,332-339
  • Place of Presentation: Berkeley, CA, USA
  • Year and Date: 2009-08-02
• [Presentation] Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters (2009)
  • Author(s): Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
  • Organizer: International Workshop on Logic and Synthesis
  • Place of Presentation: 米国カリフォルニア州
  • Year and Date: 2009-08-02
• [Presentation] Multi-Operand Adder Synthesis on FPGAs using Generalized Parallel Counters (2009)
  • Author(s): Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
  • Organizer: Proc.of International Workshop on Logic and Synthesis 2009,222-228
  • Place of Presentation: Berkeley, CA, USA
  • Year and Date: 2009-08-01
• [Presentation] A Power-aware Post-processing under depth constraint for LUT-based FPGA Technology Mapping (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Organizer: International Workshop on Logic and Synthesis
  • Place of Presentation: 米国カリフォルニア州
  • Year and Date: 2009-08-01
• [Presentation] An efficient cut enumeration for depth-optimum technology mapping for LUT-based FPGAs (2009)
  • Author(s): Taiga Takata, Yusuke Matsunaga
  • Organizer: ACM Great Lakes Symposium on VLSI,351-356
  • Place of Presentation: Boston, MA, USA
  • Year and Date: 2009-05-11
• [Presentation] Synthesis of parallel prefix adders considering switching activities (2008)
  • Author(s): Taeko Matsunaga, Sin ji Kimura, Yusuke Matsunaga
  • Organizer: In proceedings of ICCD2008,404-409
  • Place of Presentation: Tahoe, CA, USA
  • Year and Date: 2008-10-14
• [Presentation] Synthesis of parallel prefix adders considering switching activities (2008)
  • Author(s): Taeko Matsunaga, Shinji Kimura, Yusuke Matsunaga
  • Organizer: ICCD2008
  • Place of Presentation: 米国カリフォルニア州
  • Year and Date: 2008-10-14
• [Remarks] ホームページ等