A parallel programming system for various tightly coupled multi-core architectures
| Project/Area Number |
20500029
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Software
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| Research Institution | The University of Electro-Communications |
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Principal Investigator |
IWASAKI Hideya The University of Electro-Communications, 大学院・情報理工学研究科, 教授 (90203372)
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| Co-Investigator(Kenkyū-buntansha) |
SUZUKI Mitsugu 島根大学, 総合理工学部, 准教授 (50272753)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2009: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2008: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
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| Keywords | 並列プログラミングライブラリ / 並列スケルトン / マルチコア / 自動並列化 / 同期機構 / 並列化コンパイラ / 最適化 / 並列ライブ / 並列ライブラリ / メニーコア / GPGPU |
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| Research Abstract |
In this research, we have developed parallel programming systems that enable inexperienced users of parallel programming to enjoy the benefits of today's multi-core and many-core architectures. The obtained results can be summarized as follows.(1)We have developed a parallel skeleton library that offers matrices and variable-length lists.(2)We have developed a skeletal parallel framework for GPGPU programming.(3)We have developed a general and powerful framework for automatic parallelization based on matrix multiplication over a semiring.(4)We have developed a system that enables the user to statically select a suitable synchronization mechanism from a lock or a software transactional memory.
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Report
(4 results)
Research Products
(18 results)
