Design Methodology for Dynamic Reconfigurable Component Optimization
| Project/Area Number |
20500050
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Osaka University |
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Principal Investigator |
TAKEUCHI Yoshinori Osaka University, 大学院・情報科学研究科, 准教授 (70242245)
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| Co-Investigator(Kenkyū-buntansha) |
IMAI Masaharu 大阪大学, 大学院・情報科学研究科, 教授 (50126926)
SAKAMSHI Keishi 大阪大学, 大学院・情報科学研究科, 助教 (00346173)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | VLSI設計技術 / 設計最適化 / 低消費電力 / Forward Error Correction / SoC / ダイナミック・リコンフィギュラブル / ソフトウェア無線 |
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| Research Abstract |
This research studies a low power design methodology for dynamic reconfigurable components in wireless communication applications. In this research, low power and dynamically configurable 2-stage configurable decoder model is proposed. By using this model, several Forward Error Correction (FEC) decoders can be generated according to the specifications. Furthermore, by analysis of modulation and demodulation part of wireless communication systems, low bit error rate and low power system is shown to be realized by adjusting the sampling rate and computational precision of demodulation circuits.
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Report
(4 results)
Research Products
(9 results)
