Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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Research Abstract |
This research studies a low power design methodology for dynamic reconfigurable components in wireless communication applications. In this research, low power and dynamically configurable 2-stage configurable decoder model is proposed. By using this model, several Forward Error Correction (FEC) decoders can be generated according to the specifications. Furthermore, by analysis of modulation and demodulation part of wireless communication systems, low bit error rate and low power system is shown to be realized by adjusting the sampling rate and computational precision of demodulation circuits.
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