High-Level Synthesis System Autogenerating Software Compatible Hardware
Project/Area Number |
20500058
|
Research Category |
Grant-in-Aid for Scientific Research (C)
|
Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
Computer system/Network
|
Research Institution | Kwansei Gakuin University |
Principal Investigator |
ISHIURA Nagisa Kwansei Gakuin University, 理工学部, 教授 (60193265)
|
Co-Investigator(Kenkyū-buntansha) |
KANBARA Hiroyuki (財)都高度技術研究所, 研究開発部, 主任研究員 (80373497)
TOMIYAMA Hiroyuki 立命館大学, 理工学部, 教授 (80362292)
|
Project Period (FY) |
2008 – 2010
|
Project Status |
Completed (Fiscal Year 2010)
|
Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2010: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2008: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
|
Keywords | 組み込みシステム / 高位合成 / 動作合成 / HW/SW協調設計 / マルチコア / ハードウェア / ソフトウェア協調設計 / ANSI-C / 組込みシスラム設計 / ソフトウェア互換ハードウェア / ソフトウェア / ハードウェア協調設計 / 組み込みシステム設計 |
Research Abstract |
We have developed new methods of synthesizing hardware, from specified parts of ANSI-C programs, which can be called from the other parts of the programs as accelerators. We implemented a prototype of a high-level synthesizer and verified the behavior of the generated hardware on FPGA boards. We have also developed a novel concept of variable scheduling, which enables efficient adaptive execution under the existence of operations whose latencies vary depending on the values of operands or hardware status.
|
Report
(4 results)
Research Products
(17 results)