A Fundamental Study on Hardware Accelerator for SVG

Research Project

Project/Area Number	20500059
Research Category	Grant-in-Aid for Scientific Research (C)
Allocation Type	Single-year Grants
Section	一般
Research Field	Computer system/Network
Research Institution	National Institute of Informatics
Principal Investigator	YONEDA Tomohiro National Institute of Informatics, アーキテクチャ科学研究系, 教授 (30182851)
Project Period (FY)	2008 – 2010
Project Status	Completed (Fiscal Year 2010)
Budget Amount *help	¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000) Fiscal Year 2010: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000) Fiscal Year 2009: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000) Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywords	非同期式回路設計 / SVG / ハードウェア化 / 非同期式設計
Research Abstract	In this research project, we have investigated a hardware accelerator for SVG, which accepts SVG descriptions as streams, analyzes them directly, and translates them into low-level drawing command sequences based on a concurrent pipelining mechanism. This idea has been implemented as a logic circuit, and it has been functionally tested using a logic simulation tool. Furthermore, in order to decode SVG descriptions efficiently by hardware, a software preprocessor which extracts sets of objects that can be concurrently drawn without affecting the final results has been developed.