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Circuit-efficient sample-rate convertor by Fourier interpolation

Research Project

Project/Area Number 20500156
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeSingle-year Grants
Section一般
Research Field Perception information processing/Intelligent robotics
Research InstitutionKyushu Institute of Technology

Principal Investigator

KOBAYASHI Fuminori  Kyushu Institute of Technology, 大学院・情報工学研究院, 教授 (60134970)

Co-Investigator(Kenkyū-buntansha) WATANABE Minoru  静岡大学, 工学部, 准教授 (30325576)
Project Period (FY) 2008 – 2010
Project Status Completed (Fiscal Year 2010)
Budget Amount *help
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywordsディジタル・オーディオ / FPGA / 高調波歪 / クロック・ジッタ / CORDIC / クロックジッタ
Research Abstract

This project relates to SRC, sample-rate convertor, inevitable for now proliferate digital audio and video with different sampling rates. Existing SRC cannot simultaneously satisfy good performance (THD) and small circuit, because of complicated processing in the time domain. This project proposes a novel method to reconstruct signal in the frequency domain, after Fourier transform. Compared to existing methods with multi-tap filters, the method is much smaller, in the order of two, in circuit for equivalent performance.

Report

(4 results)
  • 2010 Annual Research Report   Final Research Report ( PDF )
  • 2009 Annual Research Report
  • 2008 Annual Research Report
  • Research Products

    (13 results)

All 2010 2009 2008 Other

All Presentation (12 results) Remarks (1 results)

  • [Presentation] Phase-Locked Loops-Principle and some topics2010

    • Author(s)
      小林史典
    • Organizer
      IEEE APCCAS (Asia-Pacific Conf. on Circuits And Systems)
    • Place of Presentation
      Kuala Lumpur, Malaysia
    • Year and Date
      2010-12-06
    • Related Report
      2010 Final Research Report
  • [Presentation] Phase-Locked Loops---Principle and some topics2010

    • Author(s)
      F.Kobayashi
    • Organizer
      IEEE APCCAS (Asia-Pacific Conf.on Circuits And Systems)
    • Place of Presentation
      ヒルトンホテル、クアラルンプール、マレーシア
    • Year and Date
      2010-12-06
    • Related Report
      2010 Annual Research Report
  • [Presentation] リアルタイムOSによる最短時間PLLの実装2010

    • Author(s)
      池田浩平、小林史典
    • Organizer
      平成22年度電気関係学会九州支部連合大会
    • Place of Presentation
      福岡市
    • Year and Date
      2010-09-26
    • Related Report
      2010 Final Research Report
  • [Presentation] リアルタイムOSによる最短時間PLLの実装2010

    • Author(s)
      池田浩平、小林史典
    • Organizer
      平成22年度電気関係学会九州支部連合大会
    • Place of Presentation
      九州産業大学、福岡市
    • Year and Date
      2010-09-26
    • Related Report
      2010 Annual Research Report
  • [Presentation] A Motor Speed Control System Using Dual-Loop PLL and Speed Feed-Forward/Back2010

    • Author(s)
      H.Machida, M.Kambara, K.Tanaka, F.Kobayashi
    • Organizer
      IEEE ICMA (Int.Conf. on Mechatronics and Automation)
    • Place of Presentation
      Xian, China
    • Year and Date
      2010-08-06
    • Related Report
      2010 Final Research Report
  • [Presentation] A Motor Speed Control System Using Dual-Loop PLL and Speed Feed-Forward/Back2010

    • Author(s)
      H.Machida, M.Kambara, K.Tanaka, F.Kobayashi
    • Organizer
      IEEE ICMA (Int.Conf.on Mechatronics and Automation)
    • Place of Presentation
      国際会議場、西安、中国
    • Year and Date
      2010-08-06
    • Related Report
      2010 Annual Research Report
  • [Presentation] A PLL Configuration for Reducing both Incoming and Inherent Jitters2009

    • Author(s)
      F.Kobayashi, Y.Egashira, H.Kondoh
    • Organizer
      IEEE ICECS (Int.Conf. on Electronics, Circuits and Systems)
    • Place of Presentation
      Hammamet, Tunisia
    • Year and Date
      2009-12-14
    • Related Report
      2010 Final Research Report
  • [Presentation] A PLL Configuration for Reducing both Incoming and Inherent Jitters2009

    • Author(s)
      F.Kobayashi, Y.Egashira H.Kondoh
    • Organizer
      IEEE ICECS(Int.Conf.on Electronics, Circuits and Systems)
    • Place of Presentation
      Yasmine Hammamet Hotel Hammanet, Tunisia
    • Year and Date
      2009-12-14
    • Related Report
      2009 Annual Research Report
  • [Presentation] フーリエ補間によるサンプリング・レート変換:CORDICアルゴリズムの位相近似2009

    • Author(s)
      井上学、小林史典
    • Organizer
      平成21年度電気関係学会九州支部連合大会
    • Place of Presentation
      福岡県飯塚市
    • Year and Date
      2009-09-29
    • Related Report
      2010 Final Research Report
  • [Presentation] フーリエ補間によるサンプリング・レート変換 : CORDICアルゴリズムの位相近似2009

    • Author(s)
      井上学、小林史典
    • Organizer
      平成21年度電気関係学会九州支部連合大会
    • Place of Presentation
      九州工業大学情報工学部福岡県飯塚市
    • Year and Date
      2009-09-29
    • Related Report
      2009 Annual Research Report
  • [Presentation] PLL by Interpolate Compensation2008

    • Author(s)
      Y.Nakanishi, F.Kobayashi, H.Kondoh, Low-Jitter
    • Organizer
      IEEE APCCAS (Asia -Pacific Conf. on Circuits And Sys- tems)
    • Place of Presentation
      Macau, China
    • Year and Date
      2008-12-02
    • Related Report
      2010 Final Research Report
  • [Presentation] Low-Jitter PLL by Interpolate Compensation2008

    • Author(s)
      Y. Nakanishi, F. Kobayashi, H. Kondoh
    • Organizer
      IEEE Asia-Pacific Conf. on Circuitsand Systems
    • Place of Presentation
      Venetian Resort Hotel, Macau, China
    • Year and Date
      2008-12-02
    • Related Report
      2008 Annual Research Report
  • [Remarks] ホームページ等

    • Related Report
      2010 Final Research Report

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Published: 2008-04-01   Modified: 2016-04-21  

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