Via programmable logic device with tamper resistance fabricated by EB direct writing technique applied for user authentication
| Project/Area Number |
20560340
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Ritsumeikan University |
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Principal Investigator |
FUJINO Takeshi Ritsumeikan University, 理工学部, 教授 (60367993)
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| Project Period (FY) |
2008 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2010: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2009: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | 半導体超微細化 / 先端機能デバイス / 電子ビーム描画 / プログラマブルロジック / サイドチャネルアタック / 先進機能デバイス |
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| Research Abstract |
We have studied the LSI fabrication method using EB direct writing, which is cost effective even in the small lifetime production volume. We have proposed the via programmable structured ASIC architecture "VPEX", in which any logic can be programmed by changing only 2-3 via layers.The performance and the cost of VPEX architecture were evaluated compared to standard ASIC architecture. The product of Area and Delay, which is the performance indices, is twice that of ASIC, and the total cost is lower than that of ASIC in the case that the lifetime production volume is less than several ten thousands units.
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Report
(4 results)
Research Products
(74 results)
