| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2010: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2009: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2008: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
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| Research Abstract |
The aim of this project is to identify the merit which is caused from the adoption of partial-and-dynamic reconfiguration when a high-fault-tolerant system is assumed. It reduces the amount of the logical circuit in the LSI-based system and will lead the performance improvement. Though the results were application dependent, the proposed approach can reduce the number of circuits up to 40 percents and attain higher dependability compared to naive implementation. It could be applied to embedded processors when the circuit is appropriately divided to modules. Thus, the effectiveness was able to be verified by not only special-purpose circuits but also general-purpose circuits.
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