A Study of Ultra Low-latency Network-on-Chips using Prediction and Partially Duplications
| Project/Area Number |
20700054
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | National Institute of Informatics |
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Principal Investigator |
KOIBUCHI Michihiro National Institute of Informatics, アーキテクチャ科学研究系, 准教授 (40413926)
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| Project Period (FY) |
2008 – 2009
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| Project Status |
Completed (Fiscal Year 2009)
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| Budget Amount *help |
¥2,600,000 (Direct Cost: ¥2,000,000、Indirect Cost: ¥600,000)
Fiscal Year 2009: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2008: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | 相互結合網 / システムオンチップ / トポロジ / 計算システム / ルーティング / マルチコア / チップ内ネットワーク / ルータ / メニーコア |
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| Research Abstract |
The objective of this study is to develop an innovative ultra-low latency interconnect technology in order to achieve a complex single-chip computer-system platform, such as multi-core and many-core processers. We thus proposed and evaluated (1) low-latency router architectures using a prediction and partially duplication, and (2) partially reconfiguration techniques of topology and routing for further reducing the latency with inter-router co-operations. The results of this study enable to reduce the latency of micro-systems by making the best use of the interconnection network techniques in system-level research regions, such as traditional PC clusters and massively parallel computers.
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Report
(3 results)
Research Products
(15 results)
