Budget Amount *help |
¥3,640,000 (Direct Cost: ¥2,800,000、Indirect Cost: ¥840,000)
Fiscal Year 2010: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2008: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
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Research Abstract |
A 14-bit digitally-controlled oscillator on ring topology was proposed and implemented on 0.18 mm CMOS technology. The fraction-based series, also known as Fibonacci series was employed to optimize the transistors size in a five-stage ring topology and negative skewed delay technique was used to further increase the frequency tuning. As a result, the prototype DCO demonstrates a measured frequency range up to 4.2 GHz. The proposed DCO with wideband tuning with low frequency tuning step will ease the design of an inductorless reconfigurable ADPLL for wireless transceiver where the phase noise is not strict.
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