SiGe Channel FETs for High-Performance CMOS with Advanced High-K/SiGe Gate Stack
| Project/Area Number |
20J10380
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| Research Category |
Grant-in-Aid for JSPS Fellows
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| Allocation Type | Single-year Grants |
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| Section | 国内 |
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| Review Section |
Basic Section 21060:Electron device and electronic equipment-related
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| Research Institution | The University of Tokyo |
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Principal Investigator |
李 宗恩 東京大学, 工学系研究科, 特別研究員(DC2)
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| Project Period (FY) |
2020-04-24 – 2022-03-31
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| Project Status |
Completed (Fiscal Year 2021)
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| Budget Amount *help |
¥1,700,000 (Direct Cost: ¥1,700,000)
Fiscal Year 2021: ¥800,000 (Direct Cost: ¥800,000)
Fiscal Year 2020: ¥900,000 (Direct Cost: ¥900,000)
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| Keywords | SiGe / MOS interface / high-k / interface trap states / EOT |
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| Outline of Research at the Start |
We are walking the forefront in the world which makes these famous institutions and companies focus on the most advanced technology for future AI and 5G applications. Through this research, we would like to develop a whole branch of techniques for high performance and high reliability SiGe MOSFETs.
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| Outline of Annual Research Achievements |
Ultrathin EOT TiN/Y 2 O 3 /SiGe gate stacks with EOT of 1.05 nm, the low D it of 1.1×10 11 eV -1 cm -2 , and comparable leakage current among other reported Si-cap-free SiGe MOS interfaces has been demonstrated. The improvement of the performance and reduction of S.S. have been found in the Si 0.8 Ge 0.2 /SOI pFinFETs with this gate stack.
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| Research Progress Status |
令和3年度が最終年度であるため、記入しない。
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| Strategy for Future Research Activity |
令和3年度が最終年度であるため、記入しない。
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Report
(2 results)
Research Products
(18 results)
