| Budget Amount *help |
¥18,330,000 (Direct Cost: ¥14,100,000、Indirect Cost: ¥4,230,000)
Fiscal Year 2011: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
Fiscal Year 2010: ¥4,550,000 (Direct Cost: ¥3,500,000、Indirect Cost: ¥1,050,000)
Fiscal Year 2009: ¥12,090,000 (Direct Cost: ¥9,300,000、Indirect Cost: ¥2,790,000)
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| Research Abstract |
As integrated circuit device dimensions continue to be scaled down, increasingly strict requirements are being imposed on plasma etching technology, including the precise control of profile, critical dimension, and roughness. Atomic-or nanometer-scale surface roughness has become an important issue to be resolved in the fabrication of next-generation nanoscale devices, because the roughness at the feature bottom and sidewalls affects the variability for gate or channel lengths and thus the variability in transistor performance. We have studied the formation of surface roughness during Si etching in Cl-based plasmas, through comparing experiments with numerical simulations of plasma-surface interactions and feature profile evolution on nanometer scale, using our own atomic-scale cellular model(ASCeM) and a classical molecular dynamics(MD) simulation.
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