Research on abstract modelsof FPGAs and evaluation of hardware algorithms

• Project/Area Number: 21500016
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Fundamental theory of informatics
• Research Institution: Hiroshima University
• Principal Investigator: NAKANO Koji 広島大学, 大学院・工学研究院, 教授 (30281075)
• Co-Investigator(Kenkyū-buntansha): ITO Yasuaki 広島大学, 大学院・工学研究院, 助教 (40397964)
• Project Period (FY): 2009 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000); Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000); Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000); Fiscal Year 2010: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000); Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
• Keywords: FPGA / アルゴリズム / 組込みハードウェア / ブロックRAM / ハードウェアアルゴリズム / 多倍長演算 / 暗号化

Research Abstract

We have investigated various approaches for accelerating computation using FPGAs and found a new approach that we call FDFM(Few DSP blocks and Few memory blocks) approach. Recent FPGAs have a number of embedded DSP blocks and memory blocks. The FDFM approach uses few DSP blocks and few memory blocks to install a co-processor to compute complicated computations. We have shown that RSA encryption, image pattern matching, etc. can be done very fast.

Research Products

• [Journal Article] An FPGA implementation for neural networks with the FDFM processor core approach (2013)
  • Author(s): Yuki Ago, Yasuaki Ito, Koji Nakano
  • Journal Title: International Journal of Parallel, Emergent and Distributed Systems, to appear
  • Peer Reviewed
• [Journal Article] An FPGA implementation for neural networks with the FDFM processor core approach (2013)
  • Author(s): Yuki Ago, Yasuaki Ito, Koji Nakano
  • Journal Title: International Journal of Parallel, Emergent and Distributed Systems Volume: 28 Issue: 4 Pages: 1-13
  • DOI: 10.1080/17445760.2012.684686
  • Peer Reviewed
• [Journal Article] The Parallel FDFM Processor Core Approach for CRT-based RSA Decryption (2012)
  • Author(s): Yasuaki Ito, Koji Nakano and Song Bo
  • Journal Title: International Journal of Networking and Computing Volume: Vol. 2, No. 1 Pages: 79-96
  • NAID: 130005475309
  • URL: http://www.ijnc.org/
  • Peer Reviewed
• [Journal Article] An Algorithm to Obtain Circuits with Synchronous RAMs (2012)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano and Yasuaki Ito
  • Journal Title: Journal of Communication and Computer Volume: Volume 9, Number 5 Pages: 547-559
  • URL: http://www.davidpublishing.com/
  • Peer Reviewed
• [Journal Article] A Rewriting Approach to Replace Asynchronous ROMs with Synchronous Ones for the Circuits with Cycles (2012)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Journal Title: International Journal of Networking and Computing Volume: Vol. 2, No. 2 Pages: 269-290
  • NAID: 130005475365
  • URL: http://www.ijnc.org/
  • Peer Reviewed
• [Journal Article] Efficient Exhaustive Verification of the Collatz Conjecture using DSP blocks of Xilinx FPGAs (2011)
  • Author(s): Yasuaki Ito, Koji Nakano
  • Journal Title: International Journal of Networking and Computing Volume: Vol. 1, No.1 Pages: 49-62
  • NAID: 130005091729
  • URL: http://www.ijnc.org
  • Peer Reviewed
• [Journal Article] An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA (2011)
  • Author(s): Song Bo, Kensuke Kawakami, Koji Nakano, Yasuaki Ito
  • Journal Title: International Journal of Networking and Computing Volume: Vol. 1, No.2 Pages: 277-289
  • NAID: 130005475260
  • URL: http://www.ijnc.org/
  • Peer Reviewed
• [Journal Article] A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones (2011)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Journal Title: IEICE TRANSACTIONS on Information and Systems Volume: Vol.E94-D No.12 Pages: 2378-2388
  • NAID: 10030538006
  • URL: http://dx.DOI:.org/10.1587/transinf.E94.D.2378
  • Peer Reviewed
• [Journal Article] A Graph Rewriting Approach for Converting Asynchronous ROMs into Synchronous Ones (2011)
  • Author(s): Md.Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Journal Title: IEICE TRANSACTIONS on Information and Systems Volume: E94-D Pages: 2378-2388
  • NAID: 10030538006
  • Peer Reviewed
• [Journal Article] An RSA Encryption Hardware Algorithm using a Single DSP Block and a Single Block RAM on the FPGA International Journal of Networking and Computing (2011)
  • Author(s): Song Bo Kensuke Kawaka mi, Koji Nakano, Yasuaki Ito
  • Journal Title: International Journal of Networking and Computing Volume: 1 Pages: 277-289
  • Peer Reviewed
• [Journal Article] Low-latency Connected Component Labeling Using an FPGA (2010)
  • Author(s): Yasuaki Ito and Koji Nakano
  • Journal Title: International Journal on Foundations of Computer Science Volume: Vol.21, No. 3 Issue: 03 Pages: 405-425
  • DOI: 10.1142/s0129054110007337
  • Peer Reviewed
• [Journal Article] Low-latency Connected Component Labeling Using an FPGA (2010)
  • Author(s): Yasuaki Ito, Koji Nakano
  • Journal Title: International Journal on Foundations of Computer Science Volume: 21 Pages: 405-425
  • Peer Reviewed
• [Journal Article] An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA (2010)
  • Author(s): Bo Song, Kensuke Kawakami, Koji Nakano, Yasuaki Ito
  • Journal Title: Proc.of International Conference on Networking and Computing Pages: 140-147
  • NAID: 130005475260
  • Peer Reviewed
• [Journal Article] A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits (2010)
  • Author(s): Md.Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Journal Title: Proc.of International Conference on Networking and Computing Pages: 148-157
  • Peer Reviewed
• [Journal Article] Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs (2010)
  • Author(s): Yasuaki Ito, Koji Nakano
  • Journal Title: Proc.of IPDPS Workshops Pages: 1-8
  • Peer Reviewed
• [Journal Article] A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Cojecture (2009)
  • Author(s): Yasuaki Ito, Koji Nakano
  • Journal Title: Proc.IEEE International Symposium on Parallel and Dsitributed Processing with Applications Pages: 63-70
  • Peer Reviewed
• [Journal Article] RSA encryption and decryption using the redundant numbersystem on the FPGA (2009)
  • Author(s): Koji Nakano, Kensuke Kawakami, Koji Shigemoto
  • Journal Title: Proc.IEEE International Symposium on Parallel and Distributed Processing Pages: 1-8
  • Peer Reviewed
• [Presentation] Efficient Hough Transform on the FPGA using DSP slices and Block RAMs (2013)
  • Author(s): Xin Zhou, Norihiro Tomagou, Yasuaki Ito and Koji Nakano
  • Organizer: International Parallel and Distributed Processing Systems
  • Place of Presentation: Boston, USA
• [Presentation] An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles (2011)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 大阪、日本
  • Year and Date: 2011-11-30
• [Presentation] The Parallel FDFM Processor Core Approach for Neural Networks (2011)
  • Author(s): Yuki Ago, Atsuo Inoue, Koji Nakano, and Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 大阪、日本
  • Year and Date: 2011-11-30
• [Presentation] An Algorithm to Remove Asynchronous ROMs in Circuits with Cycles, Proc.of International Conference on Networking and Computing (2011)
  • Author(s): Md.Nazrul Islam Mondal, Koji Nakano, Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 大阪
  • Year and Date: 2011-11-17
• [Presentation] The Parallel FDFM Processor Core Approach for Neural Networks (2011)
  • Author(s): Yuki Ago, Atsuo Inoue, Koji Nakano, Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 大阪
  • Year and Date: 2011-11-17
• [Presentation] CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA (2011)
  • Author(s): Bo Song, Yasuaki Ito, and Koji Nakano
  • Organizer: Workshop on Advances in Parallel and Distributed Computational Models
  • Place of Presentation: アンカレッジ、米国
  • Year and Date: 2011-05-16
• [Presentation] CRT-based Decryption using DSP blocks on the Xilinx Virtex-6 FPGA (2011)
  • Author(s): Bo Song, Yasuaki Ito, Koji Nakano
  • Organizer: International Parallel and Distributed Processmg Symposium
  • Place of Presentation: アラスカ(米国)
  • Year and Date: 2011-05-16
• [Presentation] A Perspective on the Experiential Learning of Computer Architecture (2010)
  • Author(s): Ian McLoughlin and Koji Nakano
  • Organizer: IEEE/ACM Int'l Conference on Cyber, Physical and Social Computing (CPSCom)
  • Place of Presentation: 杭州、中国
  • Year and Date: 2010-12-18
• [Presentation] An RSA Encryption Hardware Algorithm Using a Single DSP Block and a Single Block RAM on the FPGA (2010)
  • Author(s): Bo Song, Kensuke Kawakami, Koji Nakano, and Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 広島、日本
  • Year and Date: 2010-11-17
• [Presentation] A Rewriting Algorithm to Generate AROM-free Fully Synchronous Circuits (2010)
  • Author(s): Md. Nazrul Islam Mondal, Koji Nakano, and Yasuaki Ito
  • Organizer: International Conference on Networking and Computing
  • Place of Presentation: 広島、日本
  • Year and Date: 2010-11-17
• [Presentation] Applications of FPGAs for Computer System Education and Parallel Processing Research (2010)
  • Author(s): Koji Nakano
  • Organizer: International Symposium on Parallel and Distributed Processing with Applications
  • Place of Presentation: 台北、中華民国(招待講演)
  • Year and Date: 2010-09-06
• [Presentation] Efficient Exhaustive Verification of the Collatz Conjecture using DSP48E blocks of Xilinx Virtex-5 FPGAs (2010)
  • Author(s): Yasuaki Ito, Koji Nakano
  • Place of Presentation: アトランタ、米国
  • Year and Date: 2010-04-19
• [Presentation] A Hardware-Software Cooperative Approach for the Exhaustive Verification of the Collatz Cojecture (2009)
  • Author(s): Yasuaki I t o , Ko ji Nakano
  • Organizer: International Symposium on Parallel and Distributed Processing with Applications
  • Place of Presentation: 成都、中国
  • Year and Date: 2009-08-09
• [Remarks]
  • URL: http://www.cs.hiroshima-u.ac.jp/