Research on abstract modelsof FPGAs and evaluation of hardware algorithms
| Project/Area Number |
21500016
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Fundamental theory of informatics
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| Research Institution | Hiroshima University |
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Principal Investigator |
NAKANO Koji 広島大学, 大学院・工学研究院, 教授 (30281075)
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| Co-Investigator(Kenkyū-buntansha) |
ITO Yasuaki 広島大学, 大学院・工学研究院, 助教 (40397964)
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| Project Period (FY) |
2009 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥910,000 (Direct Cost: ¥700,000、Indirect Cost: ¥210,000)
Fiscal Year 2010: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2009: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | FPGA / アルゴリズム / 組込みハードウェア / ブロックRAM / ハードウェアアルゴリズム / 多倍長演算 / 暗号化 |
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| Research Abstract |
We have investigated various approaches for accelerating computation using FPGAs and found a new approach that we call FDFM(Few DSP blocks and Few memory blocks) approach. Recent FPGAs have a number of embedded DSP blocks and memory blocks. The FDFM approach uses few DSP blocks and few memory blocks to install a co-processor to compute complicated computations. We have shown that RSA encryption, image pattern matching, etc. can be done very fast.
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Report
(5 results)
Research Products
(31 results)
