Control of grain size in a low-temperature-crystallized Si film using seed layer
| Project/Area Number |
21560324
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electronic materials/Electric materials
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| Research Institution | Japan Advanced Institute of Science and Technology |
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Principal Investigator |
HORITA Susumu 北陸先端科学技術大学院大学, マテリアルサイエンス研究科, 准教授 (60199552)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2010: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
Fiscal Year 2009: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | 低温結晶化 / Si薄膜 / YSZ薄膜 / 薄膜トランジスタ / 固相成長 / 低温プロセス / 多結晶Si |
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| Research Abstract |
We investigated low-temperature solid-state crystallization(SPC) of an amorphous Si(a-Si) film on a YSZ layer which stimulates the crystallization. As a result, it is found that 1) Y/(Zr+Y) ratio is needed more than 0. 15 for low-temperature crystallization, 2) due to YSZ layer, crystallization temperature becomes lower, 3) diffusion of Zr impurity into Si and surface roughness of Si film were reduced by SPC, 4) improvement of YSZ surface quality prior to Si film deposition is needed for better crystallization, and 5) thermal expansion between layers of TFT structure should be considered on its fabrication.
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Report
(4 results)
Research Products
(43 results)
