Design Methods for Crypto LSI Implementations and Testing
| Project/Area Number |
21560370
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Waseda University |
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Principal Investigator |
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| Co-Investigator(Renkei-kenkyūsha) |
NARA Ryuta 早稲田大学, 理工学術院, 助手 (30547047)
SHI Youhua 早稲田大学, 理工学術院, 助教 (70409655)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2011: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2010: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2009: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | LSI設計 / テスト容易化設計 / スキャンチェイン / 暗号処理LSI / スキャンベース攻撃 / SD-SFF |
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| Research Abstract |
Scan test has been widely adopted as a default testing technique among most LSI designs, including crypto cores. However, these scan chains might be used as a "side channel" to recover the secret keys from the hardware implementations of cryptographic algorithms. In this research, we propose SD-SFF(State Dependent Scan Flip Flop) which significantly improves the security with ignorable design requirements for crypto hardware implementations.
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Report
(4 results)
Research Products
(25 results)
