Study on relaxed/strained semiconductor layer heterostructures fabricated by ion implantation induced relaxation technique of strained semiconductors

• Project/Area Number: 21560371
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Kanagawa University
• Principal Investigator: MIZUNO Tomohisa 神奈川大学, 理学部, 教授 (60386810)
• Co-Investigator(Kenkyū-buntansha): SAMESHIMA Toshiyuki 東京農工大学, 共生科学技術研究院, 教授 (30271597)
• Project Period (FY): 2009 – 2011
• Project Status: Completed (Fiscal Year 2011)
• Budget Amount: ¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000); Fiscal Year 2011: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2009: ¥2,210,000 (Direct Cost: ¥1,700,000、Indirect Cost: ¥510,000)
• Keywords: 電子デバイス / 集積回路 / 半導体物性 / マイクロ・ナノデバイス

Research Abstract

We have experimentally demonstrated an abrupt source heterostructure(SHOT) with relaxed/strained layers for a future high speed CMOS, using ion implantation technique. n-and p-SHOTs can be easily fabricated by the slip between the strained layer and the buried oxide on strained Si and SiGe layers, respectively, using the recoil energy of O+or H+ions.

Research Products

• [Journal Article] Postannealing Effects on Strain/Crystal Quality of Lateral Source Relaxed/Strained Layer Heterostructures Fabricated by O+Ion Implantation (2012)
  • Author(s): T. Mizuno, J. Takehi, and S. Tanabe
  • Journal Title: Jpn. J. Appl. Phys Volume: 51 Pages: 1-4
  • NAID: 210000140487
  • Peer Reviewed
• [Journal Article] Postannealing Effects on Strain/Crystal Quality of Lateral Source Relaxed/Strained Layer Heterostructures Fabricated by O^+ Ion Implantation (2012)
  • Author(s): T.Mizuno, J.Takehi, S.Tanabe
  • Journal Title: Jpn.J.Appl.Phys. Volume: 51 Issue: 4S Pages: 04DC01-04DC01
  • DOI: 10.1143/jjap.51.04dc01
  • NAID: 210000140487
  • Peer Reviewed
• [Journal Article] Experimental Study of Single Source-Heterojunction MOS Transistors(SHOTs) for Quasi-Ballistic Regime : Optimization of Source-Hetero Structures and Electron Velocity Characteristics at Low Temperature (2011)
  • Author(s): T. Mizuno, Y. Moriyama, T. Tezuka, N. Sugiyama, and S. Takagi
  • Journal Title: Jpn. J. Appl. Phys Volume: 50 Pages: 10107-10107
  • Peer Reviewed
• [Journal Article] Abrupt Lateral-Source Heterostructures with Lateral-Relaxed/Strained Layers for Ballistic CMOS Transistors Fabricated by Local O+Ion Induced Relaxation Technique of Strained Substrates (2011)
  • Author(s): T. Mizuno, M. Hasegawa, K. Ikeda, M. Nojiri, and T. Horikawa
  • Journal Title: Jpn. J. Appl. Phys Volume: 50 Pages: 2-4
  • Peer Reviewed
• [Journal Article] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors (2011)
  • Author(s): T. Mizuno, M. Hasegawa, and T. Sameshima
  • Journal Title: Key Engineering Materials Volume: 470 Pages: 72-78
  • Peer Reviewed
• [Journal Article] Lateral Source Relaxed/Strained Layer Heterostructures for Ballistic CMOS : Physical Relaxation Mechanism for Strained Layers by O+Ion Implantation (2011)
  • Author(s): T. Mizuno, J. Takehi, and S. Tanabe
  • Journal Title: Extended Abst. of SSDM Pages: 839-839
  • Peer Reviewed
• [Journal Article] Lateral Source Relaxed/Strained Layer Heterostructures for Ballistic CMOS : Physical Relaxation Mechanism for Strained Layers by O+ Ion Implantation (2011)
  • Author(s): T.Mizuno, J.Takehi, S.Tanabe
  • Journal Title: Extended Abst.of SSDM Pages: 839-840
  • Peer Reviewed
• [Journal Article] New Source Heterojunction Structures with Relaxed-/Strained-Semiconductors for Quasi-Ballistic Complementary-Metal-Oxide-Semiconductor(CMOS) Transistors : Relaxation Technique of Strained-Substrates and Design of Sub-10nm Devices (2010)
  • Author(s): Yamauchi, M. Hasegawa, T. Sameshima, and T. Tezuka
  • Journal Title: Jpn. J. Appl. Phys Volume: 49 Pages: 4-13
  • Peer Reviewed
• [Journal Article] Source Heterojunction with Relaxed/Strained-Layers for Quasi-Ballistic CMOS Transistors (2010)
  • Author(s): T. Mizuno, M. Hasegawa, and T. Sameshima
  • Journal Title: ISTESNE Pages: 66-66
  • Peer Reviewed
• [Journal Article] Abrupt Source Heterostructures with Lateral-Relaxed/Strained Layers for Quasi-Ballistic CMOS Transistors using Lateral Strain Control Technique of Strained Substrates (2010)
  • Author(s): T. Mizuno, M. Hasegawa, K. Ikeda, M. Nojiri, and T. Horikawa
  • Journal Title: Extended Abst. of SSDM Pages: 45-45
  • Peer Reviewed
• [Journal Article] Source Heterojunction with Relaxed/Strained-Layers for Quasi-Ballistic CMOS Transistors (2010)
  • Author(s): T.Mizuno, M.Hasegawa, T.Sameshima
  • Journal Title: Extend.Abst.ISTESNE Pages: 66-66
  • Peer Reviewed
• [Journal Article] Experimental Study of Single Source-Heterojunction MOS Transistors (SHOTs) for Quasi-Ballistic Regime : Optimization of Source-Hetero Structures and Electron Velocity Characteristics at Low Temperature (2010)
  • Author(s): T.Mizuno, Y.Moriyama, T.Tezuka, N.Sugiyama, S.Takagi
  • Journal Title: Jpn.J.Appl.Phys. Volume: 50
  • Peer Reviewed
• [Journal Article] Abrupt Source Heterostructures with Lateral-Relaxed/Strained Layers for Quasi-Ballistic CMOS Transistors using Lateral Strain Control Technique of Strained Substrates (2010)
  • Author(s): T.Mizuno, M.Hasegawa, K.Ikeda, M.Nojiri, T.Horikawa
  • Journal Title: Ext.Abstr.SSDM Pages: 45-46
  • Peer Reviewed
• [Journal Article] New Source Heterojunction Structures with Relaxed/Strained Semiconductors for Quasi-Ballistic Complementary Metal-Oxide-Semiconductor Transistors : Relaxation Technique of Strained Substrates and Design of Sub-10nm Devices (2010)
  • Author(s): Tomohisa Mizuno, Naoki Mizoguchi, Kotaro Tanimoto, Tomoaki Yamauchi, Mitsuo Hasegawa, Toshiyuki Sameshima, Tsutomu Tezuka
  • Journal Title: Jpn.J.Appl.Phys. 49
  • NAID: 210000068211
  • Peer Reviewed
• [Journal Article] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates (2009)
  • Author(s): T. Mizuno, N. Mizoguchi, K. Tanimoto, T. Yamauchi, T. Tezuka, and T. Sameshima
  • Journal Title: Extended Abst. of SSDM Pages: 769-769
  • Peer Reviewed
• [Journal Article] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates (2009)
  • Author(s): T.Mizuno, N.Mizoguchi, K.Tanimoto, T.Yamauchi, T.Tezuka, T.Sameshima
  • Journal Title: Ext.Abstr.SSDM Pages: 769-770
  • Peer Reviewed
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討(VI):H+イオン注入による良好な結晶性の実現 (2012)
  • Author(s): 武樋樹里亜, 赤松大夢, 阿部勇貴, 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 早稲田大学
  • Year and Date: 2012-03-17
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討(VI):H^+イオン注入による良好な結晶性の実現 (2012)
  • Author(s): 武樋樹里亜, 赤松大夢, 阿部勇貴, 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 早稲田大学
  • Year and Date: 2012-03-17
• [Presentation] Lateral Source Relaxed/Strained Layer Heterostructures for Ballistic CMOS : Physical Relaxation Mechanism for Strained Layers by O+Ion Implantation (2011)
  • Author(s): T. Mizuno
  • Organizer: International Conference on Solid State Devices and Materials
  • Place of Presentation: 名古屋
  • Year and Date: 2011-09-28
• [Presentation] Lateral Source Relaxed/Strained Layer Heterostructures for Ballistic CMOS : Physical Relaxation Mechanism for Strained Layers by O+ Ion Implantation (2011)
  • Author(s): T.Mizuno, J.Takehi, S.Tanabe
  • Organizer: SSDM
  • Place of Presentation: Aichi Industry & Labor Center
  • Year and Date: 2011-09-28
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討(V):緩和/歪みSiヘテロ構造の結晶性 (2011)
  • Author(s): 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 山形大学
  • Year and Date: 2011-09-02
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討(V):緩和/歪みSiヘテロ構造の結晶性 (2011)
  • Author(s): 水野智久, 武樋樹里亜, 田邊奨
  • Organizer: 応用物理学会
  • Place of Presentation: 山形大学
  • Year and Date: 2011-09-02
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討(IV):歪みSi層の緩和メカニズム (2011)
  • Author(s): 武樋樹里亜, 田邊奨, 有馬広記, 星野靖, 中田穣治, 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 神奈川工科大学
  • Year and Date: 2011-03-26
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討(IV):歪みSi層の緩和メカニズム (2011)
  • Author(s): 武樋樹里亜, 田邊奨, 有馬広記, 星野靖, 中田穣治, 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 神奈川工科大学
  • Year and Date: 2011-03-26
• [Presentation] Abrupt Source Heterostructures with Lateral-Relaxed/Strained Layers for Quasi-Ballistic CMOS Transistors using Lateral Strain Control Technique of Strained Substrates (2010)
  • Author(s): T. Mizuno
  • Organizer: International Conference on Solid State Devices and Materials
  • Place of Presentation: 東京大学
  • Year and Date: 2010-09-22
• [Presentation] Abrupt Source Heterostructures with Lateral-Relaxed/Strained Layers for Quasi-Ballistic CMOS Transistors using Lateral Strain Control Technique of Strained Substrates (2010)
  • Author(s): T.Mizuno, M.Hasegawa, K.Ikeda, M.Nojiri, T.Horikawa
  • Organizer: SSDM
  • Place of Presentation: Tokyo
  • Year and Date: 2010-09-22
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討(III):急峻な横方向歪み分布の実現 (2010)
  • Author(s): 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 長崎大学
  • Year and Date: 2010-09-16
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討(III):急峻な横方向歪み分布の実現 (2010)
  • Author(s): 水野智久, 長谷川光央, 野尻真士, 堀川剛
  • Organizer: 応用物理学会
  • Place of Presentation: 長崎大学
  • Year and Date: 2010-09-16
• [Presentation] Source Heterojunction with Relaxed/Strained-Layers for Quasi-Ballistic CMOS Transistors (2010)
  • Author(s): T. Mizuno
  • Organizer: International Symposium on Technology Evolution for Silicon Nano-Electronics
  • Place of Presentation: 東京工業大学
  • Year and Date: 2010-06-04
• [Presentation] Source Heterojunction with Relaxed/Strained-Layers for Quasi-Ballistic CMOS Transistors (2010)
  • Author(s): T.Mizuno, M.Hasegawa, T.Sameshima
  • Organizer: ISTESNE
  • Place of Presentation: Tokyo
  • Year and Date: 2010-06-04
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討:(II):CMOS用緩和/歪半導体構造 (2010)
  • Author(s): 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 東海大学
  • Year and Date: 2010-03-17
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討(II):CMOS用緩和/歪半導体構造 (2010)
  • Author(s): 水野智久, 長谷川光央, 鮫島俊之
  • Organizer: 応用物理学会
  • Place of Presentation: 東海大学
  • Year and Date: 2010-03-17
• [Presentation] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates (2009)
  • Author(s): T. Mizuno
  • Organizer: International Conference on Solid State Devices and Materials
  • Place of Presentation: 仙台
  • Year and Date: 2009-10-08
• [Presentation] Novel Source Heterojunction Structures with Relaxed-/Strained-Layers for Quasi-Ballistic CMOS Transistors using Ion Implantation Induced Relaxation Technique of Strained-Substrates (2009)
  • Author(s): T.Mizuno, N.Mizoguchi, K.Tanimoto, T.Yamauchi, T.Tezuka, T.Sameshima
  • Organizer: SSDM
  • Place of Presentation: Sendai
  • Year and Date: 2009-10-08
• [Presentation] 単一半導体を用いた新ソースへテロ構造の検討:(I)緩和Si/歪Siへテロ構造 (2009)
  • Author(s): 水野智久
  • Organizer: 応用物理学会
  • Place of Presentation: 富山大学
  • Year and Date: 2009-09-10
• [Presentation] 単一半導体を用いた新ソースヘテロ構造の検討:(I)緩和Si/歪Siヘテロ構造 (2009)
  • Author(s): 水野智久, 溝口直樹, 谷本光太郎, 山内知明, 鮫島俊之
  • Organizer: 応用物理学会
  • Place of Presentation: 富山大学
  • Year and Date: 2009-09-10
• [Remarks]