Proposal of test data reduction method for scan design facilitating delay fault testing
| Project/Area Number |
21700053
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Chiba University |
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Principal Investigator |
NAMBA Kazuteru Chiba University, 大学院・融合科学研究科, 助教 (60359594)
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| Project Period (FY) |
2009 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
|
| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
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| Keywords | ディペンダブルコンピューティング / 計算機システム / システムオンチップ / ディペンダブル・コンピューティング |
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| Research Abstract |
In production of VLSI, manufacturing testing is essential to detect faults. This work targets Chiba scan testing, a class of delay fault testing. This work provided two methods reducing test data volume and test application time for Chiba scan testing to reduce testing cost. One method reduces idling time of scan output. The other reorders scan FF.
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Report
(3 results)
Research Products
(7 results)
