Proposal of test data reduction method for scan design facilitating delay fault testing

• Project/Area Number: 21700053
• Research Category: Grant-in-Aid for Young Scientists (B)
• Allocation Type: Single-year Grants
• Research Field: Computer system/Network
• Research Institution: Chiba University
• Principal Investigator: NAMBA Kazuteru Chiba University, 大学院・融合科学研究科, 助教 (60359594)
• Project Period (FY): 2009 – 2010
• Project Status: Completed (Fiscal Year 2010)
• Budget Amount: ¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000); Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000); Fiscal Year 2009: ¥3,120,000 (Direct Cost: ¥2,400,000、Indirect Cost: ¥720,000)
• Keywords: ディペンダブルコンピューティング / 計算機システム / システムオンチップ / ディペンダブル・コンピューティング

Research Abstract

In production of VLSI, manufacturing testing is essential to detect faults. This work targets Chiba scan testing, a class of delay fault testing. This work provided two methods reducing test data volume and test application time for Chiba scan testing to reduce testing cost. One method reduces idling time of scan output. The other reorders scan FF.

Research Products

• [Journal Article] Chiba Scan Delay Fault Testing with Short Test Application Time (2010)
  • Author(s): K.Namba, H.Ito
  • Journal Title: J.Electronic Test. : Theory & Appl. Vol.26, No. Pages: 6667-677
  • Peer Reviewed
• [Journal Article] Chiba Scan Delay Fault Testing with Short Test Application Time (2010)
  • Author(s): 難波一輝, 伊藤秀男
  • Journal Title: Journal of Electronic Testing : Theory and Applications Volume: 26 Pages: 667-677
  • Peer Reviewed
• [Journal Article] Scan FF Reordering for Test Volume Reduction in Chiba-Scan Architecture
  • Author(s): K.Matsumoto, K.Namba, H.Ito
  • Journal Title: IPSJ Trans.Syst.LSI Des.Method 掲載予定
  • NAID: 110009598054
  • Peer Reviewed
• [Presentation] Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability, Proc. (2010)
  • Author(s): K.Matsumoto, K.Namba, H.Ito
  • Organizer: 11th IEEE Workshop RTL & High Level Test.pp.111-116
  • Place of Presentation: Shanghai SHERATON Hotel,中華人民共和国
  • Year and Date: 2010-12-06
• [Presentation] Test Vector Reduction by Reordering Flip-flops for Scan Architecture with Delay Fault Testability (2010)
  • Author(s): 松本清紀, 難波一輝, 伊藤秀男
  • Organizer: Workshop on RTL and High Level Testing
  • Place of Presentation: Shanghai SHERATON Hotel(中華人民共和国)
  • Year and Date: 2010-12-06
• [Presentation] 千葉大スキャンの接続順序変更によるテストパターン削減手法 (2010)
  • Author(s): 松本清紀, 難波一輝, 伊藤秀男
  • Organizer: FTC研究会
  • Place of Presentation: サンロード吉備路,岡山県
  • Year and Date: 2010-01-22
• [Presentation] 千葉大スキャンの接続順序変更によるテストパターン削減手法 (2010)
  • Author(s): 松本清紀, 難波一輝, 伊藤秀男
  • Organizer: 第62回FTC研究会
  • Place of Presentation: サンロード吉備路(岡山県)
  • Year and Date: 2010-01-22