Research on Test Methodology for 3D Integrated SoCs
| Project/Area Number |
21700059
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
YONEDA Tomokazu 奈良先端科学技術大学院大学, 情報科学研究科, 助教 (20359871)
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| Project Period (FY) |
2009 – 2011
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| Project Status |
Completed (Fiscal Year 2011)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2011: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2010: ¥1,170,000 (Direct Cost: ¥900,000、Indirect Cost: ¥270,000)
Fiscal Year 2009: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | テスト容易化設計 / 高品質遅延テスト / システムオンチップ / 3次元集積化 / 三次元集積化 / テストアーキテクチャ |
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| Research Abstract |
The objective of this research is to find efficient methods of test generation and design for testability to achieve high quality and low cost test for 3D integrated SoCs. In this research, I focused attention on temperature during test and test data volume for 3D integrated SoCs. Consequently, I established a test generation method to reduce temperature-variation-induced delay test quality loss and a test cost optimization method that can achieve high quality delay test with low test data volume.
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Report
(4 results)
Research Products
(20 results)
