Development of aHost-Based IPS Processor with a Reconfigurable Logic for High-Speed and Low-Power Operations
| Project/Area Number |
21700064
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| Research Category |
Grant-in-Aid for Young Scientists (B)
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| Allocation Type | Single-year Grants |
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| Research Field |
Computer system/Network
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| Research Institution | Hirosaki University |
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Principal Investigator |
SATO Tomoaki 弘前大学, 総合情報処理センター, 准教授 (00336992)
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| Project Period (FY) |
2009 – 2010
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| Project Status |
Completed (Fiscal Year 2010)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2010: ¥2,470,000 (Direct Cost: ¥1,900,000、Indirect Cost: ¥570,000)
Fiscal Year 2009: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | IDS / IPS / セキュアネットワーク / ファイアウォール / 低消費電力 / 無線LAN / 再構成可能ロジック / ウェーブパイプライン |
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| Research Abstract |
In this study, an IPS (Intrusion Prevention System) processor which is used on mobile computers is developed. The processor is composed of Firewall Logic Unit and reconfigurable logic cells. The firewall function of Firewall Logic Unit is executed by hardware logic. The unit is useful for low-power operations and reduction in number of signatures. The reconfigurable logic cells are composed of conventional logic cells and logic cells for the timing adjustment. Two 8-bit adder circuits are designed by design method for high-speed and low-power operations. One is the use of conventional logic cells and the other is the use of conventional logic cells and logic cells for the timing adjustment. The results of comparing areas of these circuits are the area of the circuit using logic cells for the timing adjustment is reduced to 28.5%.
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Report
(3 results)
Research Products
(31 results)
