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A Study on Parameter Extraction Method of Carrier Transport Properties in Layered Semiconductor Substrates

Research Project

Project/Area Number 21K04160
Research Category

Grant-in-Aid for Scientific Research (C)

Allocation TypeMulti-year Fund
Section一般
Review Section Basic Section 21050:Electric and electronic materials-related
Research InstitutionKansai University

Principal Investigator

Sato Shingo  関西大学, システム理工学部, 准教授 (60709137)

Project Period (FY) 2021-04-01 – 2024-03-31
Project Status Completed (Fiscal Year 2023)
Budget Amount *help
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2023: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2022: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
Fiscal Year 2021: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Keywordspseudo-MOS法 / 積層半導体基板 / Kelvin法 / 伝送線路モデル / 容量-電圧特性 / チャネル伝導 / 低電界移動度 / シート抵抗 / 移動度 / 界面電荷密度
Outline of Research at the Start

近年、新規材料や積層構造化により半導体素子能力の向上を模索する研究・開発が活発化しており、積層構造の界面品質に起因する電気物性の評価技術が求められている。
本研究は半導体素子形成工程を経ることなく、積層構造を有する半導体基板のキャリアの輸送特性・積層構造界面の電気的品質を、高精度に評価する手法を開発することを目的としている。様々な積層基板に適用可能な電気物性評価手法を開発することにより、半導体素子の開発速度の向上、半導体素子能力の向上に貢献する。

Outline of Final Research Achievements

This research was initiated with the aim of developing a method for accurately evaluating the electrical properties and interface quality of semiconductor substrates with a stacked structure without the fabrication process of the semiconductor device. We clarified the essential measurement configuration and substrate conditions for extracting electrical properties using the Pseudo-MOS method, which is an evaluation method for multilayered substrates. The frequency dependence of the capacitance value was measured under these conditions, and the maximum of the capacitance value at a specific frequency observed when an AC signal propagates over the channel formed near the thin-film interface was confirmed for the first time.

Academic Significance and Societal Importance of the Research Achievements

近年、活発に研究されている積層半導体基板に関して、半導体素子構造を形成することなく電気物性値を高精度に抽出する検査手法を開発することは各種材料やその積層構造開発の加速に資するものである。特に本研究を通して検査手法の高精度化に向けた測定構成・条件を明確化し、またその条件下で交流信号のチャネル上伝搬を観測できたことは界面品質に関連する検査手法の高精度化に向けた見込みを得たという点において社会的意義が大きい。

Report

(4 results)
  • 2023 Annual Research Report   Final Research Report ( PDF )
  • 2022 Research-status Report
  • 2021 Research-status Report
  • Research Products

    (9 results)

All 2024 2023 2022 2021

All Journal Article (3 results) (of which Peer Reviewed: 3 results) Presentation (6 results) (of which Int'l Joint Research: 4 results)

  • [Journal Article] Detailed analysis of the capacitance characteristic measured using the pseudo-metal–oxide–semiconductor method2024

    • Author(s)
      Sato Shingo、Yuan Yifan
    • Journal Title

      Solid-State Electronics

      Volume: 217 Pages: 108950-108950

    • DOI

      10.1016/j.sse.2024.108950

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Detailed analysis of electrical components on a layered wafer via the AC pseudo-MOS method2023

    • Author(s)
      Yuan Yifan、Sato Shingo
    • Journal Title

      Solid-State Electronics

      Volume: 210 Pages: 108811-108811

    • DOI

      10.1016/j.sse.2023.108811

    • Related Report
      2023 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Detailing Influence of Contact Condition and Island Edge on Dual-Configuration Kelvin Pseudo-MOSFET Method2021

    • Author(s)
      Mori Daigo、Nakata Iori、Matsuda Masayoshi、Sato Shingo
    • Journal Title

      IEEE Transactions on Electron Devices

      Volume: 68 Issue: 6 Pages: 2906-2911

    • DOI

      10.1109/ted.2021.3074115

    • Related Report
      2021 Research-status Report
    • Peer Reviewed
  • [Presentation] AC pseudo-MOS法による積層ウエハ上の電気的成分の詳細解析2024

    • Author(s)
      袁 一凡, 佐藤伸吾
    • Organizer
      先端科学技術シンポジウム2024
    • Related Report
      2023 Annual Research Report
  • [Presentation] Detailed analysis of electrical components on a layered wafer with an ac pseudo-MOS method,2023

    • Author(s)
      Y. Yuan, S. Sato
    • Organizer
      EuroSOI-ULIS’2023
    • Related Report
      2023 Annual Research Report
    • Int'l Joint Research
  • [Presentation] Detailed analysis of electrical components on a layered wafer with an ac pseudo-MOS method2023

    • Author(s)
      Y. Yuan, and S. Sato
    • Organizer
      9th Joint International EuroSOI Workshop and International Conference on Ultimate Integration on Silicon
    • Related Report
      2022 Research-status Report
    • Int'l Joint Research
  • [Presentation] 高精度電気物性値抽出に向けた積層半導体基板評価技術の開発2023

    • Author(s)
      袁一凡, 佐藤伸吾
    • Organizer
      第27回関西大学先端科学技術シンポジウム
    • Related Report
      2022 Research-status Report
  • [Presentation] Detailed analysis of electrical components on SOI wafer with an ac pseudo-MOS method,2022

    • Author(s)
      Y. Yuan, and S. Sato
    • Organizer
      The 2022 International Meeting for Future of Electron Devices, Kansai
    • Related Report
      2022 Research-status Report
    • Int'l Joint Research
  • [Presentation] Modeling the propagation of ac signal on the channel of the pseudo-MOS method2021

    • Author(s)
      Shingo Sato
    • Organizer
      2021 Joint International EUROSOI Workshop and International Conference on Ultimate Integration on Silicon (EuroSOI-ULIS)
    • Related Report
      2021 Research-status Report
    • Int'l Joint Research

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Published: 2021-04-28   Modified: 2025-01-30  

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