Synergistic Integration of Novel Superconductor Electronics for Energy-Efficient Computing Accelerators
| Project/Area Number |
21K04191
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 21060:Electron device and electronic equipment-related
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| Research Institution | Yokohama National University |
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Principal Investigator |
アヤラ クリストファー 横浜国立大学, 先端科学高等研究院, 特任教員(准教授) (90772195)
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| Project Period (FY) |
2021-04-01 – 2024-03-31
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| Project Status |
Completed (Fiscal Year 2023)
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| Budget Amount *help |
¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
Fiscal Year 2023: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2022: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2021: ¥1,950,000 (Direct Cost: ¥1,500,000、Indirect Cost: ¥450,000)
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| Keywords | superconductor / crypto / computing / adiabatic / sfq / aqfp / cryotron / nanowire / monolithic integration / energy-efficient / accelerators |
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| Outline of Research at the Start |
We will explore various emerging superconductor electronics to realize a practical path towards novel hybrid superconductor computing platforms that can meet the demands of today's data centric society with performance and energy-efficiency beyond what is possible with conventional technology.
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| Outline of Annual Research Achievements |
In this final year, we continued to develop methodologies and demonstrated key components for a synergistic system design of superconductor logic families. This includes a collaborative investigation with a world-class group at the Swiss Federal Institute of Technology Lausanne where a tool was developed to create optimal sequential logic circuits based on AQFP technology (10.1109/TASC.2023.3308408). To address synchronization between different logic families, a deeper characterization of the timing behavior of AQFP logic was developed (10.1109/TASC.2024.3352638). This will pave way for in-depth timing characterization of other logic families that will be co-integrated with AQFP and would increase the likelihood of successful circuit demonstration. On the end of improving the likelihood demonstrating large circuits, the analysis of circuit malfunctions due to unwanted flux trapping was performed (10.1109/TASC.2024.3354687). Thanks to this analysis, a new layout for AQFP gates with integration moats to protect the circuit from trapped flux was developed with significantly improved robustness against trapped flux. A number of to-be-published results have been produced including (1) the demonstration of combining sinusoidal and trapezoidal clocking for sequential circuits, (2) the demonstration of a large scale SHA-3 cryptoprocessing accelerator at GHz operation speeds based on using the methods and techniques developed in this research, and (3) conceptual development of a hybrid logic architecture that shows promise in the application of post-quantum cryptography.
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Report
(3 results)
Research Products
(31 results)
