| Project/Area Number |
21K11809
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Multi-year Fund |
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| Section | 一般 |
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| Review Section |
Basic Section 60040:Computer system-related
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| Research Institution | Nara Institute of Science and Technology |
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Principal Investigator |
ZHANG Renyuan 奈良先端科学技術大学院大学, 先端科学技術研究科, 准教授 (00709131)
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| Co-Investigator(Kenkyū-buntansha) |
木村 睦 奈良先端科学技術大学院大学, 先端科学技術研究科, 客員教授 (60368032)
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| Project Period (FY) |
2021-04-01 – 2024-03-31
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| Project Status |
Completed (Fiscal Year 2023)
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| Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2023: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2022: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2021: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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| Keywords | approximate computing / Neuromorphic circuits / stochastic computing / low power / artificial intelligence / スパイキングニューラルネットワーク / 確率的学習 / Non-deterministic / bisection neural network / re-configurability / efficiency / Continuous domain / parameter reduction / 確率計算 / CGRA / スパイクベース計算 |
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| Outline of Research at the Start |
本研究では、従来のデジタル厳密計算基盤からAI向け超並列曖昧計算基盤まで対応できる時・空再構成可能な演算機構の基礎研究を行う。空間軸再構成に対して独創的な二分木ニューラルネットワークにより製造後任意に解体・組立できる演算器アレイを構築する。時間軸再構成に対して非決定論的計測に基づく確率的スパイクベース計算方式を創出する。精度の制御が可能な仕組みを導入し、両者の一体化を進める。最終には精度を調整できる無駄のない厳密・非厳密混合計算基盤の実現を目指す。さらに、メムキャパシタ等新機能デバイス実装技術を加えた、開発される計算機構の小型化を探索対象とする。
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| Outline of Final Research Achievements |
The approximate computing architectures are developed in this project, which are re-configurable in temporal or spatial domain. By using the proposed technologies, the hardware (HW) costs are greatly reduced with reasonable computing accuracy. For temporal re-configurability, a series of neuromorphic computing platforms on the basis of our original topology named “DiaNet” are proposed and verified for artificial neural networks (ANNs). From various validations, the proposed architectures reduce the use of HW resources up to 95% with similar quality of service as conventional works. For spatial reconfigurable computing architectures, the asynchronous stochastic computing (ASC) methodology is proposed, implemented, and validated by various arithmetic calculations. The ASC circuits are found superior to synchronous SC on hardware efficiency and speed with similar accuracy. Moreover, the ASC platform offers rich re-configurability to trade off performance and cost post silicon.
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| Academic Significance and Societal Importance of the Research Achievements |
The technologies developed in this project are found as promising candidates of post-Moore soft computing trends for accelerating the artificial intelligence tasks. This work explores the up limit of approximate computing and reasonable scenarios for it by cutting off a great processing energy.
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