Time-Space Re-configurable Flash Computations
Project/Area Number |
21K11809
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Research Category |
Grant-in-Aid for Scientific Research (C)
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Allocation Type | Multi-year Fund |
Section | 一般 |
Review Section |
Basic Section 60040:Computer system-related
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Research Institution | Nara Institute of Science and Technology |
Principal Investigator |
ZHANG Renyuan 奈良先端科学技術大学院大学, 先端科学技術研究科, 准教授 (00709131)
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Co-Investigator(Kenkyū-buntansha) |
木村 睦 奈良先端科学技術大学院大学, 先端科学技術研究科, 客員教授 (60368032)
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Project Period (FY) |
2021-04-01 – 2024-03-31
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Project Status |
Granted (Fiscal Year 2022)
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Budget Amount *help |
¥4,160,000 (Direct Cost: ¥3,200,000、Indirect Cost: ¥960,000)
Fiscal Year 2023: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2022: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2021: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
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Keywords | Non-deterministic / bisection neural network / re-configurability / efficiency / Continuous domain / parameter reduction / 確率計算 / CGRA / スパイクベース計算 |
Outline of Research at the Start |
本研究では、従来のデジタル厳密計算基盤からAI向け超並列曖昧計算基盤まで対応できる時・空再構成可能な演算機構の基礎研究を行う。空間軸再構成に対して独創的な二分木ニューラルネットワークにより製造後任意に解体・組立できる演算器アレイを構築する。時間軸再構成に対して非決定論的計測に基づく確率的スパイクベース計算方式を創出する。精度の制御が可能な仕組みを導入し、両者の一体化を進める。最終には精度を調整できる無駄のない厳密・非厳密混合計算基盤の実現を目指す。さらに、メムキャパシタ等新機能デバイス実装技術を加えた、開発される計算機構の小型化を探索対象とする。
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Outline of Annual Research Achievements |
In this year, both of time- and space-reconfigurable computing technologies are explored in deep as planned. 1. For time-reconfigurable computing technologies, we focus on the non-deterministic computing applications in various fields such as medicine and wireless communications. By applying the proposed stochastic computing scheme, the quality of service and robustness in some real-world scenarios are both superior to the world top performances. 2. For space reconfigurable computing technologies, the DiaNet series (the third version) have been applied in various AI tasks and archived fair or superior performances with greatly reduced cost.
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Current Status of Research Progress |
Current Status of Research Progress
1: Research has progressed more than it was originally planned.
Reason
The current progress fully matches my initial proposal. All of three tiers including mechanism, circuits, and application levels have been explored, and the performances of our developed platforms are superior in some specific features. Moreover, a new technology for data-coding was developed beyond the initial plan, which accelerates the computations greatly. The relevant research progresses were published on world top-class transactions and conference such as IEEE TNNLS and IJCAI. The proposed technologies appear potentials on solving the real-world problems such as medicine and wireless communications. The next step of this project is well indicated on the basis of progress of this year. From the current results, the “calculator free NN inference” becomes feasible as initially planned.
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Strategy for Future Research Activity |
Firstly, the quantum-spike coding methodology will be explored. We are going to start from some toy-examples such as conventional neural networks. Two schemes including one-shot observation and statistic observation are verified to perform regression and pattern recognition. Then, we will migrate this coding methodology into our DiaNet. Secondly and simultaneously, more series of DiaNet (so far, till version 3.1) and flash computing architecture are expected to evolve. As soon as above techniques ready, we might migrate some existing tensor computing structures such as systolic ring by partitioning the DiaNet into reasonable pieces. As the further step rooting on this project, it is expected to develop the CMOS-superconductor hybrid computing platforms.
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Report
(2 results)
Research Products
(13 results)