| Project/Area Number |
21K17719
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| Research Category |
Grant-in-Aid for Early-Career Scientists
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| Allocation Type | Multi-year Fund |
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| Review Section |
Basic Section 60040:Computer system-related
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| Research Institution | Tohoku University |
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Principal Investigator |
李 涛 東北大学, 電気通信研究所, 助教 (20794952)
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| Project Period (FY) |
2021-04-01 – 2025-03-31
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| Project Status |
Granted (Fiscal Year 2023)
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| Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2022: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2021: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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| Keywords | Neural Networks / Error-resilient / STT-MRAM / Brain-inspired Processor / Energy-efficient / Error Resilient / Error-resillient / Power Reduction / DNNs |
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| Outline of Research at the Start |
This research introduces a power reduction technique for the spin-transfer torque magnetic random-access memory (STT-MRAM) based brain-inspired processor design using fault tolerance of error-resilient deep neural networks (DNNs) to reduce the working current of spin-transfer torque magnetic tunnel junction (STT-MTJ). It is expected that the full function of DNNs can be implemented on a low-power consumption brain-inspired processor while sustaining an acceptable performance for the emerging applications in modern Internet-of-Everything (IoE) society.
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| Outline of Annual Research Achievements |
Regarding our progress in the fiscal year 2023, we are exploring methods to reduce the power consumption of devices by combining the error resilience characteristics of DNNs with the switching characteristics of non-volatile devices. Theoretically, we have clarified the relationship between the fault tolerance of DNNs and the switching current of non-volatile devices, and experimentally, we have demonstrated a technique to reduce power consumption without compromising the accuracy of DNNs by introducing random errors into low 8-bit DNN parameters. The experimental results show that by inverting a random 20% of the binary digits, we can reduce the power consumption by 5.63%, and by inverting 100% of the binary digits, we can save 34.84% of energy. Furthermore, by incorporating the error map of six practical STT-MRAM chips, which have a maximum error rate of 0.00868, into the low 8-bit parameters of DNNs, there is no impact on their accuracy under the switching current equivalent to a 100% switching probability (with a maximum loss of 0.00067). The average top-1 and top-5 accuracy decreases for MobileNet are respectively 0.000355, 0.00079, 0.000670, and 0.000310, which has only a minimal impact on their industrial applications.
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| Current Status of Research Progress |
Current Status of Research Progress
3: Progress in research has been slightly delayed.
Reason
One of the challenges we faced was the delay in receiving publication results for our preliminary findings. This waiting period has slightly impacted the project's progress and the ability to share our discoveries with the wider scientific community for feedback and collaboration. Furthermore, the duration required to prepare the experimental environments exceeded initial expectations. Challenges included sourcing specific hardware components, setting up hardware circuit simulations, and ensuring the experimental setup could accurately measure the impact on power consumption and performance.
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| Strategy for Future Research Activity |
In the next step, we will continue to investigate the relationship between power consumption in non-volatile devices and the error tolerance characteristics of neural networks. Specifically, we aim to explore effective mathematical models to verify how optimal error tolerance can significantly reduce the power consumption of non-volatile devices. Following theoretical analysis, we will validate the impact of reducing the current in non-volatile devices on the power consumption and performance of MTJ cells from the perspective of hardware circuit simulation.
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