A Novel Power Reduction Technique Using Error-resilient Deep Neural Networks for STT-MRAM Based Energy-efficient Brain-inspired Processor Design
Project/Area Number |
21K17719
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Research Category |
Grant-in-Aid for Early-Career Scientists
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Allocation Type | Multi-year Fund |
Review Section |
Basic Section 60040:Computer system-related
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Research Institution | Tohoku University |
Principal Investigator |
李 涛 東北大学, 工学研究科, 助教 (20794952)
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Project Period (FY) |
2021-04-01 – 2024-03-31
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Project Status |
Granted (Fiscal Year 2022)
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Budget Amount *help |
¥4,680,000 (Direct Cost: ¥3,600,000、Indirect Cost: ¥1,080,000)
Fiscal Year 2022: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
Fiscal Year 2021: ¥2,340,000 (Direct Cost: ¥1,800,000、Indirect Cost: ¥540,000)
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Keywords | Neural Networks / Error-resilient / STT-MRAM / Brain-inspired Processor / Energy-efficient / Error Resilient / Error-resillient / Power Reduction / DNNs |
Outline of Research at the Start |
This research introduces a power reduction technique for the spin-transfer torque magnetic random-access memory (STT-MRAM) based brain-inspired processor design using fault tolerance of error-resilient deep neural networks (DNNs) to reduce the working current of spin-transfer torque magnetic tunnel junction (STT-MTJ). It is expected that the full function of DNNs can be implemented on a low-power consumption brain-inspired processor while sustaining an acceptable performance for the emerging applications in modern Internet-of-Everything (IoE) society.
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Outline of Annual Research Achievements |
This year, we continued our study on the adaptive quantization algorithm and validated its influence on AI chip performance in terms of algorithms and circuit architecture. A novel adaptive and low-power quantization technique and systematically validates its effectiveness from the algorithm to the hardware module for industrial IoT applications, covering precise navigation for autonomous vehicles and accurate classification utilizing deep neural networks. The proposed quantization method merges an adaptive conversion function from floating-point to fixed-point binaries with an adaptive radix-point determination function, ensuring adequate resolution and minimal error loss of the fixed-point inputs to the edge AI modules. In addition, a hybrid signed convolution module with the architecture of an unsigned divide-and-conquer multiplier is proposed to improve the functional diversity and energy efficiency of artificial intelligence accelerators based on STT-MRAM. The proposed multiplier framework enables different multiplication modes, considerably enhancing the multiplier's versatility for next-generation AI accelerators.
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Current Status of Research Progress |
Current Status of Research Progress
3: Progress in research has been slightly delayed.
Reason
The applicant has achieved substantial advancements in the design of hardware circuits for brain-inspired processors using the error-resilient neural network algorithm. Nevertheless, the impact of COVID-19 on the semiconductor deficit has caused delays in the purchase of some hardware devices, therefore delaying the hardware system's development.
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Strategy for Future Research Activity |
This year, the applicant achieved major achievements in designing quantization and convolutional circuits for brain-inspired processors. Throughout the next year, the applicant will keep developing the subsequent design of the brain-inspired processor circuit, such as the activation function approximation and hardwareization.
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Report
(2 results)
Research Products
(5 results)