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Power Adjustment Testing for Next-Generation Low-Power LSI Circuits

Research Project

Project/Area Number 22300017
Research Category

Grant-in-Aid for Scientific Research (B)

Allocation TypeSingle-year Grants
Section一般
Research Field Computer system/Network
Research InstitutionKyushu Institute of Technology

Principal Investigator

WEN Xiaoqing  九州工業大学, 情報工程学院, 教授 (20250897)

Co-Investigator(Kenkyū-buntansha) KAJIHARA Seiji  九州工業大学, 情報工学研究院, 教授 (80252592)
MIYASE Kohei  九州工業大学, 情報工学研究院, 助教 (30452824)
Project Period (FY) 2010 – 2012
Project Status Completed (Fiscal Year 2012)
Budget Amount *help
¥6,500,000 (Direct Cost: ¥5,000,000、Indirect Cost: ¥1,500,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2010: ¥4,420,000 (Direct Cost: ¥3,400,000、Indirect Cost: ¥1,020,000)
KeywordsLSIテスト / 低電力テスト / テスト電力調整 / 遅延テスト / 微小遅延故障 / 活性化パス / 高品質化 / 高信頼化
Research Abstract

There are two major problems in LSI testing, namely decreasing test yield due to excessive delay along sensitized paths and decreasing test quality due to inadequate delay along sensitized paths. In this research, a novel scheme has been established, which dynamically adjusts regional power dissipation in the neighborhood of sensitized paths to minimize its impact on test yield and test quality. This scheme of power adjustment testing is expected to contribute to higher test yield and better test quality.

Report

(4 results)
  • 2012 Annual Research Report   Final Research Report ( PDF )
  • 2011 Annual Research Report
  • 2010 Annual Research Report
  • Research Products

    (59 results)

All 2013 2012 2011 2010 Other

All Journal Article (9 results) (of which Peer Reviewed: 9 results) Presentation (45 results) (of which Invited: 2 results) Book (2 results) Remarks (3 results)

  • [Journal Article] Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains2012

    • Author(s)
      S. Wu, L. -T. Wang, X. Wen, Z. Jiang, W. -B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C. -M. Li, and J. -L. Huang
    • Journal Title

      ACM Transactions on Design Automation of Electronic Systems

      Volume: Vol. 17, Issue 4, Article No. 48

    • Related Report
      2012 Final Research Report
    • Peer Reviewed
  • [Journal Article] Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns2012

    • Author(s)
      H. Salmani, W. Zhao, M. Tehranipoor, S. Chacravarty, P. Girard, and X. Wen
    • Journal Title

      ASP Journal of Lower Power Electronics

      Volume: Vol. 8, No. 2 Pages: 248-258

    • Related Report
      2012 Annual Research Report 2012 Final Research Report
    • Peer Reviewed
  • [Journal Article] Launch-on-Shift Test Generation for Testing Scan Designs Containing Synchronous and Asynchronous Clock Domains2012

    • Author(s)
      S. Wu, L.-T. Wang, X. Wen, Z. Jiang, W.-B. Jone, M. S. Hsiao, L. Tan, Y. Zhang, C.-M. Li, J.-L. Huang
    • Journal Title

      ACM Transactions on Design Automation of Electronic Systems

      Volume: Vol. 17, Iss. 4 Issue: 4 Pages: 1-16

    • DOI

      10.1145/2348839.2348852

    • Related Report
      2012 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing2011

    • Author(s)
      K. Miyase, K. Noda, H. Ito, K. Hatayama, T. Aikyo, Y. Yamato, H. Furukawa, X. Wen, and S. Kajihara
    • Journal Title

      IEICE Trans. Inf. & Syst.

      Volume: Vol. E94-D, No. 6 Pages: 1216-1226

    • NAID

      10029805011

    • Related Report
      2012 Final Research Report
    • Peer Reviewed
  • [Journal Article] A GA-Based X-Filling for Reducing Launch Switching Activity toward Specific Objectives in At-Speed Scan Testing2011

    • Author(s)
      Y.Yamato, X.Wen, R.Miyase, H.Furukawa, S.Kajihara
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E94-D Issue: 4 Pages: 833-840

    • DOI

      10.1587/transinf.E94.D.833

    • NAID

      10029506602

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2011 Annual Research Report
    • Peer Reviewed
  • [Journal Article] Distribution-Controlled X-Identification for Effective Reduction of Launch-Induced IR-Drop in At-Speed Scan Testing2011

    • Author(s)
      K.Miyase, K.Noda, H.Ito, K.Hatayama, T.Aikyo, Y.Yamato, H.Furukawa, X.Wen, S.Kaiihara
    • Journal Title

      IEICE Transactions on Information and Systems

      Volume: E94.D Issue: 6 Pages: 1216-1226

    • DOI

      10.1587/transinf.E94.D.1216

    • NAID

      10029805011

    • ISSN
      0916-8532, 1745-1361
    • Related Report
      2011 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing2010

    • Author(s)
      K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, A. Takashima, H. Furukawa, K. Noda, H. Ito, K. Hatayama, T. Aikyo, and K. K. Saluja
    • Journal Title

      IEICE Trans. Inf. & Syst.

      Volume: Vol. E93-A, No. 7 Pages: 1309-1318

    • NAID

      10027367482

    • Related Report
      2012 Final Research Report
    • Peer Reviewed
  • [Journal Article] A Study of Capture-Safe Test Generation Flow for At-Speed Testing2010

    • Author(s)
      K.Miyase, X.Wen, S.Kajihara, Y.Yamato, A.Takashima, H.Furukawa, K.Noda, N.Ito, K.Hatayama, T.Aikyo, K.Saluja
    • Journal Title

      IEICE Trans.Inf.& Syst.

      Volume: E93-A Pages: 1309-1318

    • NAID

      10027367482

    • Related Report
      2010 Annual Research Report
    • Peer Reviewed
  • [Journal Article] A Comprehensive Analysis of Transition Fault Coverage and Test Power Dissipation for LOS and LOC Schemes2010

    • Author(s)
      F.Wu, L..Dilillo, A.Bosio, P.Girard, S.Pravossoudovitch, A.Virazel, M.Tehranipoor, X.Wen, N.Ahmed
    • Journal Title

      ASP Journal of Lower Power Electronics

      Volume: 6 Pages: 359-374

    • Related Report
      2010 Annual Research Report
    • Peer Reviewed
  • [Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013

    • Author(s)
      K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, and L.-T. Wang
    • Organizer
      Proc. 26th Intl. Conf. on VLSI Design
    • Place of Presentation
      Pune, India
    • Related Report
      2012 Final Research Report
  • [Presentation] On Guaranteeing Capture Safety in At-Speed Scan Testing With Broadcast-Scan-Based Test Compression2013

    • Author(s)
      K. Enokimoto, X. Wen, K. Miyase, J.-L. Huang, S. Kajihara, L.-T. Wang
    • Organizer
      26th Intl. Conf. on VLSI Design
    • Place of Presentation
      Pune, India
    • Related Report
      2012 Annual Research Report
  • [Presentation] Fault Detection with Optimum March Test Algorithm2012

    • Author(s)
      N.A.Zakariz, W.Z.W.Hasan, I.A.Halin, R.M.Sidek, X.Wen
    • Organizer
      IEEE International Conference on Intelligent Systems, Modeling and Simulation
    • Place of Presentation
      Kota Kinabalu, Malaysia
    • Year and Date
      2012-02-08
    • Related Report
      2011 Annual Research Report
  • [Presentation] 実速度スキャンテストにおける高品質なキャプチャ安全性保障型テスト生成について2012

    • Author(s)
      西田優一郎, 温暁青, 工藤雅幸, 宮瀬紘平, 梶原誠司
    • Organizer
      FTC研究会
    • Place of Presentation
      日本大分県
    • Year and Date
      2012-01-21
    • Related Report
      2011 Annual Research Report
  • [Presentation] New Test Partition Approach for Rotating Test with Lower Rate2012

    • Author(s)
      S.Wang, S.Kajihara, Y.Sato, K.Miyase, X.Wen
    • Organizer
      FTC研究会
    • Place of Presentation
      日本大分県
    • Year and Date
      2012-01-19
    • Related Report
      2011 Annual Research Report
  • [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012

    • Author(s)
      Y. -T. Lin, J. -L. Huang, and X. Wen
    • Organizer
      Proc. VLSI Test Technology Workshop
    • Place of Presentation
      Yilan, Taiwan
    • Year and Date
      2012-01-10
    • Related Report
      2012 Final Research Report
  • [Presentation] Estimation of the Amount of Don' t-Care Bits in Test Vectors2012

    • Author(s)
      K. Miyase, S. Kajihara, and X. Wen
    • Organizer
      Proc. IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Final Research Report
  • [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012

    • Author(s)
      Y. -T. Lin, J. -L Huang, and X. Wen
    • Organizer
      Proc. IEEE Asian Test Symp
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Final Research Report
  • [Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012

    • Author(s)
      K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, and S. Kajihara
    • Organizer
      Proc. IEEE VLSI Test Symp.
    • Place of Presentation
      Hawaii, USA
    • Related Report
      2012 Final Research Report
  • [Presentation] Estimation of the Amount of Don't-Care Bits in Test Vectors2012

    • Author(s)
      K. Miyase, S. Kajihara, X. Wen
    • Organizer
      IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Annual Research Report
  • [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012

    • Author(s)
      Y.-T. Lin, J.-L Huang, X. Wen
    • Organizer
      IEEE Asian Test Symp.
    • Place of Presentation
      Niigata, Japan
    • Related Report
      2012 Annual Research Report
  • [Presentation] A Transition Isolation Scan Cell Design for Low Shift and Capture Power2012

    • Author(s)
      Y.-T. Lin, J.-L Huang, X. Wen
    • Organizer
      VLSI Test Technology Workshop
    • Place of Presentation
      Yilan, Taiwan
    • Related Report
      2012 Annual Research Report
  • [Presentation] A Novel Capture-Safety Checking Method for Multi-Clock Designs and Accuracy Evaluation with Delay Capture Circuits2012

    • Author(s)
      K. Miyase, M. Aso, R. Ootsuka, X. Wen, H. Furukawa, Y. Yamato, K, Enokimoto, S. Kajihara
    • Organizer
      IEEE VLSI Test Symp.
    • Place of Presentation
      Hawaii, USA
    • Related Report
      2012 Annual Research Report
  • [Presentation] Power-Aware Testing: The Next Stage2012

    • Author(s)
      X. Wen
    • Organizer
      IEEE European Test Symposium
    • Place of Presentation
      Annecy, France
    • Related Report
      2012 Annual Research Report
    • Invited
  • [Presentation] Towards the Next-Generation Power-Aware Testing Technologies2012

    • Author(s)
      X. Wen
    • Organizer
      CMOS Emerging Technologies Conference
    • Place of Presentation
      Vancouver, Canada
    • Related Report
      2012 Annual Research Report
    • Invited
  • [Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011

    • Author(s)
      K.Miyase, H.Tanaka, K.Enokimoto, X.Wen, S.Kajihara
    • Organizer
      IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Jaipur, India
    • Year and Date
      2011-11-26
    • Related Report
      2011 Annual Research Report
  • [Presentation] Power-Aware Test Pattern Generation for At-Speed LOS Testing2011

    • Author(s)
      A.Bosio, L.Dilillo, P.Girard, A.Todri, A.Virazel, K.Miyase, X.Wen
    • Organizer
      IEEE Asian Test Symposium
    • Place of Presentation
      New Delhi, India
    • Year and Date
      2011-11-23
    • Related Report
      2011 Annual Research Report
  • [Presentation] Efficient BDD-based Fault Simulation in Presence of Unknown Values2011

    • Author(s)
      M.A.Kochte, S.Rundu, K.Miyase, X.Wen, H.-J.Wunderlich
    • Organizer
      IEEE Asian Test Symposium
    • Place of Presentation
      New Delhi, India
    • Year and Date
      2011-11-23
    • Related Report
      2011 Annual Research Report
  • [Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011

    • Author(s)
      K.Miyase, U.Uchinodan, K.Enokimoto, Y.Yamato, X.Wen, S.Kajihara, F.Wu, L.Dilillo, A.Bosio, P.Girard
    • Organizer
      IEEE Asian Test Symposium
    • Place of Presentation
      New Delhi, India
    • Year and Date
      2011-11-22
    • Related Report
      2011 Annual Research Report
  • [Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures2011

    • Author(s)
      M.A.Kochte, K.Miyase, X.Wen, S.Kajihara, Y.Yamato, K.Enokimoto, H.-J.Wunderlich
    • Organizer
      IEEE International Symposium on Low Power Electronics and Design
    • Place of Presentation
      Fukuoka, Japan
    • Year and Date
      2011-08-01
    • Related Report
      2011 Annual Research Report
  • [Presentation] VLSI Testing and Test Power2011

    • Author(s)
      X. Wen
    • Organizer
      Proc. Workshop on Low Power System on Chip (SoC)
    • Place of Presentation
      Orlando, USA
    • Year and Date
      2011-07-28
    • Related Report
      2012 Final Research Report
  • [Presentation] VLSI Testing and Test Power2011

    • Author(s)
      X.Wen
    • Organizer
      IEEE Workshop on Low Power System on Chip (SoC)
    • Place of Presentation
      Orlando, USA(招待講演)
    • Year and Date
      2011-07-28
    • Related Report
      2011 Annual Research Report
  • [Presentation] Layout-Aware Pattern Evaluation and Analysis for Power-Safe Application of TDF Patterns2011

    • Author(s)
      H.Salmani, W.Zhao, M.Tehranipoor, S.Chacravarty, X.Wen
    • Organizer
      IEEE Intl.Workshop on Impact of Low-Power design on Test and Reliability
    • Place of Presentation
      Trodheim, Norway
    • Year and Date
      2011-05-27
    • Related Report
      2011 Annual Research Report
  • [Presentation] Mapping Test Power to Functional Power Through Smart X-Filling for LOS Scheme2011

    • Author(s)
      F.Wu, L.Dilillo, A.Bosio, P.Girard, M.Tehranipoor, K.Miyase, X.Wen, N.Ahmed
    • Organizer
      IEEE Intl.Workshop on Impact of Low-Power design on Test and Reliability
    • Place of Presentation
      Trodheim, Norway
    • Year and Date
      2011-05-27
    • Related Report
      2011 Annual Research Report
  • [Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing2011

    • Author(s)
      X.Wen, K.Enokimoto, K.Miyase, Y.Yamato, M.Kochte, S.Kajihara, P.Girard, M.Tehranipoor
    • Organizer
      IEEE VLSI Test Symposium
    • Place of Presentation
      Dana Point, USA
    • Year and Date
      2011-05-03
    • Related Report
      2011 Annual Research Report
  • [Presentation] Power Reduction Through X-filling of Transition Fault Test Vectors for LOS Testing2011

    • Author(s)
      F.Wu, L.Dilillo, A.Bosio, P.Girard, S.Pravossoudovitch, A.Virazel, M.Tehranipoor, K.Miyase, X.Wen, N.Ahmed
    • Organizer
      6th International Conference on Design & Technology of Integrated Systems in Nanoscale Era
    • Place of Presentation
      Athens, Grace
    • Year and Date
      2011-04-06
    • Related Report
      2011 Annual Research Report
  • [Presentation] Additional Path Delay Fault Detection with Adaptive Test Data2011

    • Author(s)
      K. Miyase, H. Tanaka, K. Enokimoto, X. Wen, and S. Kajihara
    • Organizer
      Proc. IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Jaipur, India
    • Related Report
      2012 Final Research Report
  • [Presentation] Effective Launch Power Reduction for Launch-Off-Shift Scheme with Adjacent-Probability-Based X-Filling2011

    • Author(s)
      K. Miyase, U. Uchinodan, K. Enokimoto, Y. Yamato, X. Wen, S. Kajihara, F. Wu, L. Dilillo, A. Bosio, and P. Girard
    • Organizer
      Proc. IEEE Asian Test Symp.
    • Place of Presentation
      New Delhi, India
    • Related Report
      2012 Final Research Report
  • [Presentation] Efficient BDD-based Fault Simulation in Presence of Unknown Values2011

    • Author(s)
      M. A. Kochte, S. Kundu, K. Miyase, X. Wen, and H. -J. Wunderlich
    • Organizer
      Proc. IEEE Asian Test Symp.
    • Place of Presentation
      New Delhi, India
    • Related Report
      2012 Final Research Report
  • [Presentation] Towards the Next Generation of Low-Power Test Technologies2011

    • Author(s)
      X. Wen
    • Organizer
      Proc. IEEE Int' 1. Conf. on ASIC
    • Place of Presentation
      Hong Kong, China
    • Related Report
      2012 Final Research Report
  • [Presentation] Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing2011

    • Author(s)
      Y. -T. Lin, J. -L. Huang, and X. Wen
    • Organizer
      Proc. IEEE Intl. Test Conf.
    • Place of Presentation
      Anaheim, USA
    • Related Report
      2012 Final Research Report
  • [Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing2011

    • Author(s)
      Y. Yamato, X. Wen, M. A. Kochte, K. Miyase, S. Ka j ihara, and L. -T. Wang
    • Organizer
      Proc. IEEE Intl. Test Conf.
    • Place of Presentation
      Anaheim, USA
    • Related Report
      2012 Final Research Report
  • [Presentation] SAT-based Capture-Power Reduction for At-Speed Broadcast-Scan-Based Test Compression Architectures2011

    • Author(s)
      M. A. Kochte, K. Miyase, X. Wen, S. Ka j ihara, Y. Yamato, K. Enokimoto, and H.-J. Wunderlich
    • Organizer
      Proc. IEEE Intl. Symp. on Low Power Electronics and Design
    • Place of Presentation
      Fukuoka, Japan
    • Related Report
      2012 Final Research Report
  • [Presentation] Power-Aware Test Generation with Guaranteed Launch Safety for At-Speed Scan Testing2011

    • Author(s)
      X. Wen, K. Enokimoto, K. Miyase, Y. Yamato, M. Kochte, S. Ka j ihara, P. Girard, and M. Tehranipoor
    • Organizer
      Proc. IEEE VLSI Test Symp.
    • Place of Presentation
      Dana Point, USA
    • Related Report
      2012 Final Research Report
  • [Presentation] X-Identification of Transition Delay Fault Tests for Launch-off Shift Scheme2010

    • Author(s)
      K.Miyase, F.Wu, L.Dilillo, A.Bosio, P.Girard, X.Wen, S.Kajihara
    • Organizer
      IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Shanghai, China
    • Year and Date
      2010-12-06
    • Related Report
      2010 Annual Research Report
  • [Presentation] Power-Aware Test for Low-Power Devices2010

    • Author(s)
      X.Wen
    • Organizer
      IEEE Workshop on RTL and High Level Testing
    • Place of Presentation
      Shanghai, China
    • Year and Date
      2010-12-05
    • Related Report
      2010 Annual Research Report
  • [Presentation] Power-Aware Test for Low-Power LSI Circuits2010

    • Author(s)
      X.Wen
    • Organizer
      International Workshop on Microelectronics Assembling and Packaging
    • Place of Presentation
      Fukuoka, Japan
    • Year and Date
      2010-11-18
    • Related Report
      2010 Annual Research Report
  • [Presentation] Low-Capture-Power Post-Processing Test Vectors for Test Compression Using SAT Solver2010

    • Author(s)
      K K.Miyase, M.A.Kochte, X.Wen, S.Kajihara, H.-J.Wunderlich
    • Organizer
      IEEE Workshop on Defect and Date Driven Testing
    • Place of Presentation
      Austin, USA
    • Year and Date
      2010-11-05
    • Related Report
      2010 Annual Research Report
  • [Presentation] Towards the Next Generation of Low-Power Test Technologies2010

    • Author(s)
      X.Wen
    • Organizer
      IEEE International Test on ASIC
    • Place of Presentation
      Amoi, China(招待講演)
    • Year and Date
      2010-10-27
    • Related Report
      2011 Annual Research Report
  • [Presentation] Low-Aware Test for Low-Power Devices2010

    • Author(s)
      X.Wen
    • Organizer
      IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
    • Place of Presentation
      Kyoto, Japan
    • Year and Date
      2010-10-07
    • Related Report
      2010 Annual Research Report
  • [Presentation] Architectures for Testing 3D Chips Using Time-Division Demultiplexing/Multiplexing2010

    • Author(s)
      L.-T.Wang, N.A.Touba, M.S.Hsiao, J.-L.Huang, C.-M.Li, S.Wu, X.Wen, M.Bhattarai, F.Li, Z.Jiang
    • Organizer
      IEEE International Workshop on Testing Three-Dimensional Stacked Integrated Circuits
    • Place of Presentation
      Anaheim, USA
    • Year and Date
      2010-09-23
    • Related Report
      2011 Annual Research Report
  • [Presentation] A Novel Scan Segmentation Design Method for Avoiding Shift Timing Failure in Scan Testing2010

    • Author(s)
      Y.Yamato, X.Wen, M.A.Kochte, K.Miyase, S.Kajihara, L.-T.Wang
    • Organizer
      IEEE International Test Conference
    • Place of Presentation
      Anaheim, USA
    • Year and Date
      2010-09-21
    • Related Report
      2011 Annual Research Report
  • [Presentation] Clock-Gating-Aware Low Launch WSA Test Pattern Generation for At-Speed Scan Testing2010

    • Author(s)
      Y.-T.Lin, J.-L.Huang, X.Wen
    • Organizer
      IEEE International Test Conference
    • Place of Presentation
      Anaheim, USA
    • Year and Date
      2010-09-20
    • Related Report
      2011 Annual Research Report
  • [Presentation] Test Power Reduction : From Artillery Fire to Sniper Fire2010

    • Author(s)
      X.Wen
    • Organizer
      International Workshop on the Impact of Low-Power Design on Test and Reliability
    • Place of Presentation
      Prague, Czech
    • Year and Date
      2010-05-27
    • Related Report
      2010 Annual Research Report
  • [Presentation] Power-Aware Test for Low-Power LSI Circuits2010

    • Author(s)
      X.Wen
    • Organizer
      CMOS Emerging Technologies Workshop
    • Place of Presentation
      Whistler, Canada
    • Year and Date
      2010-05-19
    • Related Report
      2010 Annual Research Report
  • [Book] Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, Advanced Circuits for Emerging Technologies2012

    • Author(s)
      X. Wen and Y. Zorian, John Wiley & Sons
    • Publisher
      New Jersey
    • Related Report
      2012 Final Research Report
  • [Book] Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits, in Advanced Circuits for Emerging Technologies2012

    • Author(s)
      X. Wen, Y. Zorian
    • Total Pages
      18
    • Publisher
      Part IV Circuit Testing, Chapter 20: Low-Power Testing for Low-Power LSI Circuits
    • Related Report
      2012 Annual Research Report
  • [Remarks]

    • URL

      http://aries3a.cse.kyutech.ac.jprwen/

    • Related Report
      2012 Final Research Report
  • [Remarks]

    • URL

      http://aries3a.cse.kyutech.ac.jp/~wen/

    • Related Report
      2011 Annual Research Report
  • [Remarks]

    • URL

      http://aries3a.cse.kyutech.ac.jp/~wen/

    • Related Report
      2010 Annual Research Report

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Published: 2010-08-23   Modified: 2019-07-29  

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