Acceleration of Timing Analysis using Monte Carlo Methods
| Project/Area Number |
22360143
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| Research Category |
Grant-in-Aid for Scientific Research (B)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Electron device/Electronic equipment
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| Research Institution | Kyoto University |
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Principal Investigator |
SATO Takashi 京都大学, 大学院・情報学研究科, 教授 (20431992)
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| Co-Investigator(Kenkyū-buntansha) |
OCHI Hiroyuki 京都大学, 大学院・情報学研究科, 准教授 (40264957)
TSUTSUI Hiroshi 京都大学, 大学院・情報学研究科, 助教 (30402803)
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| Project Period (FY) |
2010 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥18,850,000 (Direct Cost: ¥14,500,000、Indirect Cost: ¥4,350,000)
Fiscal Year 2012: ¥5,590,000 (Direct Cost: ¥4,300,000、Indirect Cost: ¥1,290,000)
Fiscal Year 2011: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2010: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000)
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| Keywords | 集積回路設計技術 / CAD / タイミング解析 / モンテカルロ法 / 集積回路設計 / 電子回路CAD |
|---|
| Research Abstract |
Timing constraint is one of the most important objectives in advanced integrated circuit design. In this project, acceleration of the timing analysis is studied. Based on the measurements on test-chips, variability- and degradation-aware device models have been first proposed to accurately handle timing information of miniaturized devices. A new algorithm of timing analysis has then been implemented on a hardware, thorough which by more than ten times acceleration has been achieved while maintaining advantages of Monte Carlo based methods that can handle arbitrary delay distribution.
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Report
(4 results)
Research Products
(77 results)
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[Presentation] Path clustering for adaptive test2010
Author(s)
Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato
Organizer
IEEE VLSI test symposium (VTS)
Place of Presentation
Santa Cruz, USA
Related Report
