| Budget Amount *help |
¥18,850,000 (Direct Cost: ¥14,500,000、Indirect Cost: ¥4,350,000)
Fiscal Year 2012: ¥5,590,000 (Direct Cost: ¥4,300,000、Indirect Cost: ¥1,290,000)
Fiscal Year 2011: ¥5,720,000 (Direct Cost: ¥4,400,000、Indirect Cost: ¥1,320,000)
Fiscal Year 2010: ¥7,540,000 (Direct Cost: ¥5,800,000、Indirect Cost: ¥1,740,000)
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| Research Abstract |
Timing constraint is one of the most important objectives in advanced integrated circuit design. In this project, acceleration of the timing analysis is studied. Based on the measurements on test-chips, variability- and degradation-aware device models have been first proposed to accurately handle timing information of miniaturized devices. A new algorithm of timing analysis has then been implemented on a hardware, thorough which by more than ten times acceleration has been achieved while maintaining advantages of Monte Carlo based methods that can handle arbitrary delay distribution.
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