Extracting The Regions with No Memory Accessfor High-level Synthesis
| Project/Area Number |
22500034
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Software
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| Research Institution | Tokyo University of Science |
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Principal Investigator |
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| Project Period (FY) |
2010 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥4,290,000 (Direct Cost: ¥3,300,000、Indirect Cost: ¥990,000)
Fiscal Year 2012: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
Fiscal Year 2011: ¥1,430,000 (Direct Cost: ¥1,100,000、Indirect Cost: ¥330,000)
Fiscal Year 2010: ¥1,820,000 (Direct Cost: ¥1,400,000、Indirect Cost: ¥420,000)
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| Keywords | コンパイラ / 高位合成 / コード最適化 / 静的単一代入形式 / 網羅型データフロー解析 / 要求駆動型データフロー解析 / キャッシュ効率化 / 大域値番号付け / 部分冗長除去 / スカラー置換 / キャッシュ最適化 / 部分無用コード除去 / ＣＯＩＮＳ / 並列化 / FPGA |
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| Research Abstract |
In order to decrease the number of memory accesses, we have implemented a technique aggregating array references in continuous for improving cache-efficiency, and a technique applying the scalar replacement, which replaces array references with register references over some iterations of a loop, to an entire program. Also, in order to improve the efficiency of these techniques, we have developed the demand-driven partial redundancy elimination based on the global value numbering, and then have developed the demand-driven partial dead code elimination applying the demand-driven property to the partial dead code elimination.
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Report
(4 results)
Research Products
(15 results)
