Development of methods for testing and diagnosing faults on clock lines in system LSIs

• Project/Area Number: 22500048
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Computer system/Network
• Research Institution: Ehime University
• Principal Investigator: HIGAMI Yoshinobu 愛媛大学, 大学院・理工学研究科, 准教授 (40304654)
• Co-Investigator(Kenkyū-buntansha): TAKAHASHI Hiroshi 愛媛大学, 大学院・理工学研究科, 教授 (80226878)
• Project Period (FY): 2010 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000); Fiscal Year 2012: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000); Fiscal Year 2011: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000); Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
• Keywords: ディペンダブルコンピューティング / 論理回路の故障検査 / LSIの故障診断 / 故障検査 / システムLSI / クロック信号線 / 遅延故障 / テストパターン生成 / LSIの設計・テスト / 故障診断 / 論理回路

Research Abstract

：I n this research, we have developed a testing and a diagnosis method for system LSIs. Targets are delay faults and bridging faults on clock lines. The method locates a fault site in a circuit under diagnosis, and it applies a simulation-based approach. The effectiveness of the method are confirmed by the computer simulation for benchmark circuits.

Research Products

• [Journal Article] Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool (2012)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: IEICE Trans. on Inf. & Systems Volume: vol. E95-D Pages: 1093-1100
  • NAID: 10030942163
• [Journal Article] Diagnosis of Bridging Faults at Gated Clock Lines (2012)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications
• [Journal Article] Diagnosis for Bridging Faults on Clock Lines (2012)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: Proc. Pacific Rim Int. Symposium on Dependable Computing Pages: 135-144
  • DOI: 10.1109/prdc.2012.15
• [Journal Article] Generation of Diagnostic Tests for Transition Faults Using a Stuck-at ATPG Tool (2012)
  • Author(s): Yoshinobu Higami
  • Journal Title: IEICE Trans. on Information and Systems Volume: E95-D Pages: 1093-1100
  • NAID: 10030942163
  • Peer Reviewed
• [Journal Article] Diagnosis of Bridging Faults at Gated Clock Lines (2012)
  • Author(s): Yoshinobu Higami
  • Journal Title: Proc. Int. Technical Conf. on Circuits/Systems, Computers and Communications Volume: -
  • Peer Reviewed
• [Journal Article] Diagnosis for Bridging Faults on Clock Lines (2012)
  • Author(s): Yoshinobu Higami
  • Journal Title: Proc. Pacific Rim Int. Symposium on Dependable Computing Volume: - Pages: 135-144
  • Peer Reviewed
• [Journal Article] Enhancement of Clock Delay Faults Testing (2011)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: Proc. European Test Symposium Pages: 216-216
  • DOI: 10.1109/ets.2011.27
• [Journal Article] On Detecting Transition Faults in the Presence of Clock Delay Faults (2011)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: Proc. Asian Test Symposium Pages: 1-6
  • DOI: 10.1109/ats.2011.33
• [Journal Article] Fault Simulation and Test Generation for Clock Delay Faults (2011)
  • Author(s): Y. Higami, H. Takahashi, S. Kobayashi and K. Saluja
  • Journal Title: Proc. Asia and South Pacific Design Automation Conference Pages: 799-805
  • DOI: 10.1109/aspdac.2011.5722299
• [Journal Article] Fault Simulation and Test Generation for Clock Delay Faults (2011)
  • Author(s): Y.Higami, H.Takahashi, S.Kobayashi, K.K.Saluja
  • Journal Title: Proc.of Asia and South Pacific Design Automation Conference Pages: 799-805
  • Peer Reviewed
• [Presentation] クロック信号線の遅延故障に対するテスト生成について (2010)
  • Author(s): 樋上喜信, 高橋寛, 小林真也, Kewal K.Saluja
  • Organizer: FTC研究会
  • Place of Presentation: 埼玉県秩父郡
  • Year and Date: 2010-07-16
• [Presentation] FTC 研究会 (2010)
  • Author(s): 樋上喜信,高橋寛,小林真也,Kewal K. Saluja
  • Organizer: クロック信号線の遅延故障に対するテスト生成について