Development of methods for testing and diagnosing faults on clock lines in system LSIs
| Project/Area Number |
22500048
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| Research Category |
Grant-in-Aid for Scientific Research (C)
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| Allocation Type | Single-year Grants |
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| Section | 一般 |
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| Research Field |
Computer system/Network
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| Research Institution | Ehime University |
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Principal Investigator |
HIGAMI Yoshinobu 愛媛大学, 大学院・理工学研究科, 准教授 (40304654)
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| Co-Investigator(Kenkyū-buntansha) |
TAKAHASHI Hiroshi 愛媛大学, 大学院・理工学研究科, 教授 (80226878)
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| Project Period (FY) |
2010 – 2012
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| Project Status |
Completed (Fiscal Year 2012)
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| Budget Amount *help |
¥3,250,000 (Direct Cost: ¥2,500,000、Indirect Cost: ¥750,000)
Fiscal Year 2012: ¥650,000 (Direct Cost: ¥500,000、Indirect Cost: ¥150,000)
Fiscal Year 2011: ¥1,560,000 (Direct Cost: ¥1,200,000、Indirect Cost: ¥360,000)
Fiscal Year 2010: ¥1,040,000 (Direct Cost: ¥800,000、Indirect Cost: ¥240,000)
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| Keywords | ディペンダブルコンピューティング / 論理回路の故障検査 / LSIの故障診断 / 故障検査 / システムLSI / クロック信号線 / 遅延故障 / テストパターン生成 / LSIの設計・テスト / 故障診断 / 論理回路 |
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| Research Abstract |
：I n this research, we have developed a testing and a diagnosis method for system LSIs. Targets are delay faults and bridging faults on clock lines. The method locates a fault site in a circuit under diagnosis, and it applies a simulation-based approach. The effectiveness of the method are confirmed by the computer simulation for benchmark circuits.
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Report
(4 results)
Research Products
(12 results)
