Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanism
Project/Area Number |
22560326
|
Research Category |
Grant-in-Aid for Scientific Research (C)
|
Allocation Type | Single-year Grants |
Section | 一般 |
Research Field |
Electron device/Electronic equipment
|
Research Institution | Japan Advanced Institute of Science and Technology |
Principal Investigator |
KANEKO Mineo 北陸先端科学技術大学院大学, 情報科学研究科, 教授 (00185935)
|
Project Period (FY) |
2010 – 2012
|
Project Status |
Completed (Fiscal Year 2012)
|
Budget Amount *help |
¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000)
Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000)
Fiscal Year 2011: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000)
Fiscal Year 2010: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
|
Keywords | 集積回路 / 製造ばらつき / セットアップ・ホールド / タイミング・スキュー / 高位合成 / タイミングテスト / 資源割り当て / PDE調整 / PDE / 製造後チューニング / タイミングばらつき / クロック・スキュー / 順序彩色 / ILP |
Research Abstract |
LSIs suffers variations during fabrication process, and timing fault due to those variations is one of the biggest problems for current and future advanced LSIs. Timing skew tuning after fabrication (Post Silicon Skew Tuning) is a key technology to overcome such timing problem and to draw the best possible performance of individual chip. Register transfer level design optimizations of LSIs with PSST mechanism and skew tuning algorithms together with optimized timing test schedule have been developed in this project.
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Report
(4 results)
Research Products
(64 results)