Robustness against delay variations and design optimization for datapath circuits with post silicon timing tuning mechanism

• Project/Area Number: 22560326
• Research Category: Grant-in-Aid for Scientific Research (C)
• Allocation Type: Single-year Grants
• Section: 一般
• Research Field: Electron device/Electronic equipment
• Research Institution: Japan Advanced Institute of Science and Technology
• Principal Investigator: KANEKO Mineo 北陸先端科学技術大学院大学, 情報科学研究科, 教授 (00185935)
• Project Period (FY): 2010 – 2012
• Project Status: Completed (Fiscal Year 2012)
• Budget Amount: ¥3,770,000 (Direct Cost: ¥2,900,000、Indirect Cost: ¥870,000); Fiscal Year 2012: ¥1,300,000 (Direct Cost: ¥1,000,000、Indirect Cost: ¥300,000); Fiscal Year 2011: ¥780,000 (Direct Cost: ¥600,000、Indirect Cost: ¥180,000); Fiscal Year 2010: ¥1,690,000 (Direct Cost: ¥1,300,000、Indirect Cost: ¥390,000)
• Keywords: 集積回路 / 製造ばらつき / セットアップ・ホールド / タイミング・スキュー / 高位合成 / タイミングテスト / 資源割り当て / PDE調整 / PDE / 製造後チューニング / タイミングばらつき / クロック・スキュー / 順序彩色 / ILP

Research Abstract

LSIs suffers variations during fabrication process, and timing fault due to those variations is one of the biggest problems for current and future advanced LSIs. Timing skew tuning after fabrication (Post Silicon Skew Tuning) is a key technology to overcome such timing problem and to draw the best possible performance of individual chip. Register transfer level design optimizations of LSIs with PSST mechanism and skew tuning algorithms together with optimized timing test schedule have been developed in this project.

Research Products

• [Journal Article] A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: EICE Trans. Fundamentals Volume: Vol.E95-A, No.12 Pages: 2330-2337
  • NAID: 10031161367
  • Peer Reviewed
• [Journal Article] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of IEEE International Symposium on Circuits and Systems Volume: - Pages: 1664-1667
  • Peer Reviewed
• [Journal Article] Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of ACM/IEEE Great Lakes Symposium on VLSI Volume: - Pages: 79-82
  • Peer Reviewed
• [Journal Article] A Formal Approach to Optimal Register Binding with Ordered Clocking for Clock-Skew Tolerant Datapaths (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: IEICE Trans. Fundamentals Volume: E95-A Pages: 2330-2337
  • NAID: 10031161367
  • Peer Reviewed
• [Journal Article] Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of IEEE Mid-West Symposium on Circuits and Systems Volume: - Pages: 631-634
  • Peer Reviewed
• [Journal Article] Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests (2012)
  • Author(s): Mineo Kaneko, Li Jiang
  • Journal Title: Proceedings of IEEE International Symposium on Circuits and Systems Volume: - Pages: 125-128
  • Peer Reviewed
• [Journal Article] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning (2012)
  • Author(s): Mineo Kaneko
  • Journal Title: Proceedings of IEEE International Conference on Computer Design Volume: - Pages: 460-465
  • Peer Reviewed
• [Journal Article] Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of 17th Asia-South-Pacific Design Automation Conference Pages: 239-244
  • Peer Reviewed
• [Journal Article] Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of International Symposium on Quality Electronic Design Pages: 778-783
  • Peer Reviewed
• [Journal Article] Backward Data Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: IEICE Trans. Fundamentals Volume: Vol.E94-A, No.4 Pages: 1067-1081
  • NAID: 10029503424
  • Peer Reviewed
• [Journal Article] Framework for Latch-Based High-Level Synthesis using Minimum-Delay Compensation (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: IPSJ Transactions on System LSI Design Methodology Volume: Vol. 4 Pages: 232-244
  • NAID: 130002073517
  • Peer Reviewed
• [Journal Article] Flexible Test Scheduling for an Asynchronous On-chip Interconnect Through Special Data Transfer (2011)
  • Author(s): Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
  • Journal Title: IEICE Trans. Fundamentals Volume: Vol. E94-A, No. 12 Pages: 2563-2570
  • NAID: 10030533654
  • Peer Reviewed
• [Journal Article] Backward-Data-Direction Clocking and Relevant Optimal Register Assignment in Datapath Synthesis (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko, Tsuyoshi Iwagaki
  • Journal Title: IEICE Transactions on Fundamentals Volume: Vol.E94-A Pages: 1067-1081
  • NAID: 10029503424
  • Peer Reviewed
• [Journal Article] Variable-Duty-Cycle Scheduling in Double-Edge-Triggered Flip-Flop-Based High-Level Synthesis (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of IEEE International Symposium on Circuits and Systems Pages: 550-553
  • Peer Reviewed
• [Journal Article] Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew-Adjustability (2011)
  • Author(s): Mineo Kaneko, Keisuke Inoue
  • Journal Title: Proceedings of ACM Great Lakes Symposium on VLSI Pages: 307-312
  • Peer Reviewed
• [Journal Article] peration Scheduling Considering Time Borrowing for High-Performance Latch-Based Circuits (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of 9th IEEE International NEW Circuits and System Conference Pages: 245-248
  • Peer Reviewed
• [Journal Article] Early Planning for RT-Level Delay Insertion during Clock Skew Aware Register Binding (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip Pages: 154-159
  • Peer Reviewed
• [Journal Article] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling (2011)
  • Author(s): Mineo Kaneko
  • Journal Title: Proceedings of International Symposium on Quality Electronic Design Pages: 189-195
  • Peer Reviewed
• [Journal Article] Ordered Coloring for Skew Adjustability-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Journal Title: 電子情報通信学会VLSIgx計技術研究会技術報告 Volume: VLS2010-42 Pages: 1-6
  • NAID: 110008107081
• [Journal Article] ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Journal Title: 電子情報通信学会VLSI設計技術研究会技術報告 Volume: VLD2010-75 Pages: 131-136
  • NAID: 110008152357
• [Journal Article] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法 (2010)
  • Author(s): 党羽, 金子峰雄
  • Journal Title: 電子情報通信学会VLSI設計技術研究会技術報告 Volume: VLD2010-133 Pages: 99-104
  • NAID: 110008689550
• [Journal Article] Heuristic and Exact Resource Binding Algorithms for Storage Optimization Using Flip-flops and Latches
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Journal Title: IEICE Trans. Fundamentals
  • NAID: 130003370707
  • Peer Reviewed
• [Presentation] Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning (2013)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 沖縄県那覇市
  • Year and Date: 2013-03-06
• [Presentation] Test Planning for Post-Silicon Skew Tuning Based on Graph Partitioning (2013)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI設計技術研究会
  • Place of Presentation: 沖縄県那覇市青年会館
• [Presentation] Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning (2012)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 福岡県福岡市
  • Year and Date: 2012-11-27
• [Presentation] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning (2012)
  • Author(s): Mineo Kaneko
  • Organizer: Proceedings of IEEE International Conference on Computer Design (ICCD)
  • Place of Presentation: Montreal, CANADA
  • Year and Date: 2012-10-03
• [Presentation] Mineo Kaneko, Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis (2012)
  • Author(s): Keisuke Inoue
  • Organizer: Proceedings of IEEE Mid-West Symposium on Circuits and Systems
  • Place of Presentation: Boise, Idaho, USA
  • Year and Date: 2012-08-07
• [Presentation] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of IEEE International Symposium on Circuits and Systems
  • Place of Presentation: Seoul, Korea
  • Year and Date: 2012-05-22
• [Presentation] Post Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests (2012)
  • Author(s): Mineo Kaneko, Li Jiang
  • Organizer: Proceedings of IEEE International Symposium on Circuits and Systems
  • Place of Presentation: Seoul, Korea
  • Year and Date: 2012-05-21
• [Presentation] Optimal Register-Type Selection during Resource Binding in Flip-Flop/ Latch-Based High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of ACM/IEEE Great Lakes Symposium on VLSI (GLSVLSI)
  • Place of Presentation: Salt Lake City, Utah, USA
  • Year and Date: 2012-05-03
• [Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Scheduling-Aware High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of International Symposium on Quality Electronic Design (ISQED)
  • Place of Presentation: Santa Clara, California, USA
  • Year and Date: 2012-03-21
• [Presentation] 製造後スキュー調整性を最大化するRTL 資源割当法 (2012)
  • Author(s): 春田洋佑, 金子峰雄
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 大分県別府市
  • Year and Date: 2012-03-06
• [Presentation] 製造後スキュー調整性を最大化するRTL資源割当法 (2012)
  • Author(s): 春田洋佑, 金子峰雄
  • Organizer: 電子情報通信学会VLSI設計技術研究会,VLD2011-127,pp.43-48
  • Place of Presentation: ビーコンプラザ(大分県別府市)
  • Year and Date: 2012-03-06
• [Presentation] Performance-Driven Register Write Inhibition in High-Level Synthesis under Strict Maximum-Permissible Clock Latency Range (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of 17th Asia-South-Pacific Design Automation Conference (ASP-DAC 2012)
  • Place of Presentation: Sydney, Australia
  • Year and Date: 2012-01-30
• [Presentation] Dynamic Timing-Test Scheduling for Post-Silicon Skew Tuning (2012)
  • Author(s): Mineo Kaneko
  • Organizer: 電 子情報通信学会 VLSI設計技術研究会
  • Place of Presentation: 福岡県福岡市九州大学
• [Presentation] Optimal Register-Type Selection during Resource Binding in Flip-Flop/Latch-Based High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: ACM/IEEE Great Lakes Symposium on VLSI
  • Place of Presentation: 米国 ソルトレイクシティ
• [Presentation] Reliable and Low-Power Clock Distribution Using Pre- and Post-Silicon Delay Adaptation in High-Level Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: IEEE International Symposium on Circuits and Systems
  • Place of Presentation: 韓国 ソウル
• [Presentation] Post-Silicon Skew Tuning Algorithm Utilizing Setup and Hold Timing Tests (2012)
  • Author(s): Mineo Kaneko, Li Jiang
  • Organizer: IEEE International Symposium on Circuits and Systems
  • Place of Presentation: 韓国 ソウル
• [Presentation] Statistical Timing-Yield Driven Scheduling and FU Binding in Latch-Based Datapath Synthesis (2012)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: IEEE Mid-West Symposium on Circuits and Systems
  • Place of Presentation: 米国 アイダホ
• [Presentation] Timing-Test Scheduling for Constraint-Graph Based Post-Silicon Skew Tuning (2012)
  • Author(s): Mineo Kaneko
  • Organizer: IEEE International Conference on Computer Design
  • Place of Presentation: カナダ モントリオール
• [Presentation] A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning (2011)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 宮崎県宮崎市
  • Year and Date: 2011-11-29
• [Presentation] A Basic Study on Timing-Test Scheduling for Post-Silicon Skew Tuning (2011)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会VLSI設計技術研究会,VLD2011-79,DC2011-55 pp.159-164
  • Place of Presentation: ニューウェルシティ宮崎(宮崎県宮崎市)
  • Year and Date: 2011-11-29
• [Presentation] Early Planning for RT-Level Delay Insertion during Clock Skew-Aware Register Binding (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of IFIP/IEEE International Conference on Very Large Scale Integration and System-on-Chip (VLSI-SoC) 2011
  • Place of Presentation: Kowloon, Hong Kong
  • Year and Date: 2011-10-03
• [Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Optimization (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 福島県会津市
  • Year and Date: 2011-09-27
• [Presentation] Register Binding and Domain Assignment for Multi-Domain Clock Skew Optimization (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: 電子情報通信学会VLSI設計技術研究会,VLD2011-51,pp.61-66
  • Place of Presentation: 会津大学(福島県)
  • Year and Date: 2011-09-27
• [Presentation] LSI設計技術の最前線--タイミングばらつきを克服する-- (2011)
  • Author(s): 金子峰雄
  • Organizer: 電気関係学会北陸支部連合大会
  • Place of Presentation: 福井大学(福井県)(招待講演)
  • Year and Date: 2011-09-17
• [Presentation] タイミングテストを利用するLSI 製造後スキュー調整アルゴリズム (2011)
  • Author(s): 李健, 金子峰雄
  • Organizer: 電子情報通信学会 基礎・境界ソサイエティ大会
  • Place of Presentation: 北海道札幌市
  • Year and Date: 2011-09-16
• [Presentation] タイミングテストを利用するLSI製造後スキュー調整アルゴリズム (2011)
  • Author(s): 李健, 金子峰雄
  • Organizer: 電子情報通信学会基礎・境界ソサイエティ大会,講演A-3-17,基礎・境界講演論文集p.91
  • Place of Presentation: 北海道大学(北海道)
  • Year and Date: 2011-09-16
• [Presentation] On the NP-Hardness of Minimum-Period Register Binding (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: 電子情報通信学会 基礎・境界ソサイエティ大会
  • Place of Presentation: 北海道札幌市
  • Year and Date: 2011-09-15
• [Presentation] On the NP-Hardness of Minimum-Period Register Binding (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: 電子情報通信学会基礎・境界ソサイエティ大会講演A-1-15,基礎・境界講演論文集p.15
  • Place of Presentation: 北海道大学(北海道)
  • Year and Date: 2011-09-15
• [Presentation] Operation Scheduling Considering Time Borrowing for High-Performance Latch Based Circuits (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of 9th IEEE International NEW Circuits and System Conference (NEWCAS 2011)
  • Place of Presentation: Bordeaux,France
  • Year and Date: 2011-06-28
• [Presentation] Variable-Duty-Cycle Scheduling in Double Edge Triggered Flip-Flop-Based High-Level Synthesis (2011)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS)
  • Place of Presentation: Rio de Janeiro, Brazil
  • Year and Date: 2011-05-15
• [Presentation] Ordered Coloring-Based Resource Binding for Datapaths with Improved Skew Adjustability (2011)
  • Author(s): Mineo Kaneko, Keisuke Inoue
  • Organizer: Proceedings of ACM Great Lakes Symposium on VLSI (GLSVLSI 2011)
  • Place of Presentation: Lausanne, Switzerland
  • Year and Date: 2011-05-04
• [Presentation] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling (2011)
  • Author(s): Mineo Kaneko
  • Organizer: Proceedings of International Symposium on Quality Electronic Design (ISQED), IEEE Catalog No. CFP11250-CDR
  • Place of Presentation: Santa Clara, CA, USA
  • Year and Date: 2011-03-15
• [Presentation] A Complete Framework of Simultaneous Functional Unit and Register Binding with Skew Scheduling (2011)
  • Author(s): Mineo Kaneko
  • Organizer: International Symposium on Quality Electronic Design
  • Place of Presentation: 米国サンタクララ
  • Year and Date: 2011-03-15
• [Presentation] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法 (2011)
  • Author(s): 党羽, 金子峰雄
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 沖縄県那覇市
  • Year and Date: 2011-03-03
• [Presentation] 速度性能とタイミングスキュー調整特性に優れたデータパスの合成手法 (2011)
  • Author(s): 党羽, 金子峰雄
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 沖縄県那覇市
  • Year and Date: 2011-03-02
• [Presentation] Optimal Register Assignment with Minimum-Delay Compensation for Latch-Based Design (2010)
  • Author(s): Keisuke Inoue, Mineo Kaneko
  • Organizer: Proceedings of 2010 IEEE Asia Pacific Conference on Circuits and Systems
  • Place of Presentation: Kuala Lumpur, Malaysia
  • Year and Date: 2010-12-06
• [Presentation] An Approach to Test Scheduling for Asynchronous On-Chip Interconnects Using Integer Programming (2010)
  • Author(s): Tsuyoshi Iwagaki, Eiri Takeda, Mineo Kaneko
  • Organizer: Proceedings of IEEE Eleventh Workshop on RTL and High Level Testing (WRTLT'10)
  • Place of Presentation: Shanghai, P.R. China
  • Year and Date: 2010-12-05
• [Presentation] ILP Approach to Extended Ordered Coloring for Skew Adjustably-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLSI 設計技術研究会
  • Place of Presentation: 福岡県福岡市
  • Year and Date: 2010-12-01
• [Presentation] ILP Approach to Extended Ordered Coloring for Skew Adjustability-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 福岡県福岡市
  • Year and Date: 2010-12-01
• [Presentation] Ordered Coloring for Skew Adjustability-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会 VLD 研究会
  • Place of Presentation: 京都府京都市
  • Year and Date: 2010-09-27
• [Presentation] Ordered Coloring for Skew Adjustability-Aware Resource Binding (2010)
  • Author(s): Mineo Kaneko
  • Organizer: 電子情報通信学会VLSI設計技術研究会
  • Place of Presentation: 京都府京都市
  • Year and Date: 2010-09-27
• [Presentation] 耐遅延変動データパス合成における性能を考慮した可変式順序制約付レジスタ割り当て (2010)
  • Author(s): 井上恵介,金子峰雄
  • Organizer: 情報処理学会 DA シンポジウム
  • Place of Presentation: 愛知県豊橋市
  • Year and Date: 2010-09-03