| Budget Amount *help |
¥13,390,000 (Direct Cost: ¥10,300,000、Indirect Cost: ¥3,090,000)
Fiscal Year 2012: ¥5,460,000 (Direct Cost: ¥4,200,000、Indirect Cost: ¥1,260,000)
Fiscal Year 2011: ¥3,900,000 (Direct Cost: ¥3,000,000、Indirect Cost: ¥900,000)
Fiscal Year 2010: ¥4,030,000 (Direct Cost: ¥3,100,000、Indirect Cost: ¥930,000)
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| Research Abstract |
This research project developed a high-performance cryptographic processor with a state-of-the-art tamper resistance capability and its design methodology. More precisely, we designed a processor architecture specified for exponentiation operation which is an integral part of public-key cryptographic operation, and developed an RSA processor highly resistant to side-channel attacks. In addition, we demonstrated the validity of the developed processor through an exhaustive set of experiments on side-channel attacks (i.e., chosen-message power/EM analysis attacks and fault injection attacks) against a prototype implementation of the developed processor. Moreover, we developed an automatic generator which generates RSA processors depending on various design specifications.
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